Abstract: A broadband switching matrix having M.times.N crosspoint switches is arranged into a selected number of groups of vertically cascaded stages in which adjacent groups are interconnected with expansion stages. An input signal switched from row to column in a particular group propagates through the remaining stages in that group and then propagates successively through the expansion stages in each following group before reaching an output port. In another array configuration, a set of N multiplexers arranged in parallel each receive N input signals and provide a single output signal at a respective output port. The multiplexers are constructed from 2:1 selector elements which are arranged in a vertical tree configuration having log.sub.2 N cascaded stages. Each multiplexer has the same number of stages and hence selector elements. Both broadband switching arrays are designed so that each switch drives only one other switch in the array, thereby minimizing capacitive loading and maximizing propagation speed.

Abstract: Electrical circuitry providing a compatible interface between ECL logic level of -1.6 and -0.8 volts and CMOS logic levels of 0 and +5 volts. Voltage sources of -3.7 and +1.3 volts are provided for supplying operating voltages to the CMOS circuitry in order to set the threshold voltage CMOS inverters at -1.2 volts, the threshold voltage of ECL logic circuits.

Abstract: A broadband switching array for equalizing the delay experienced by input signals as they propagate through their respective swtiching hpaths, and for providing output signals having uniform logical polarities. A cascaded set of delay means is connected to each of the input ports of the array in accordance with the amount of additional delay that is needed to accomplish equalization. Likewise, a cascaded set of inverter means is connected to each ouput port so that each switching path performs a common number of inversion operations, thereby allowing the output signals to have the same logical polarity.

Abstract: A system for transmitting digital signals over a transmission line including a driver of an inverter employing CMOS FET's and a termination of an inverter employing CMOS FET's. A sense/control circuit at the termination senses changes in the operating condition of the driver inverter and in response thereto controls the operating condition of the termination inverter. Under steady state conditions the termination inverter establishes the appropriate voltage at an output connection coupled thereto without dissipating any power.

Abstract: A crosspoint switching array of a matrix of crosspoint switches connected in rows and columns. Each crosspoint switch includes an MOS inverter circuit for propagating a digital signal from crosspoint-to-crosspoint along its row. Each crosspoint switch includes a first MOS switch connected to the preceding crosspoint switch in the column and a second MOS switch connected to its row. The second switch is activated to connect the row to the column at a particular crosspoint. Otherwise, the first switch is activated to connect the crosspoint switch to the preceding crosspoint switch in the column. The output of the first or second switch is applied to an MOS inverter circuit for driving the following crosspoint switch in the column.

Abstract: In a data transmission system including a central subsystem coupled by transmission lines of different lengths to a plurality of remote subsystems, methods and apparatus for synchronizing responses to messages transmitted by the central subsystem to compensate for different line delays are provided. The messages are transmitted by the central subsystem during the first portion of a frame, while the responses are transmitted by the remote subsystems during a second portion of the frame. In each of the remote subsystems, a compensation delay equal to a maximum line delay associated with the longest of the transmission lines less an actual line delay associated with the transmission line connected to that remote subsystem is determined. The response to the message is then delayed by the compensation delay so that the responses from each remote subsystem arrive at the central subsystem delayed by the maximum time delay.

Abstract: A digital switching system is described for providing time division multiplexed digital communication of parallel sequential signals of N words each of M bit length between N telephone data subscribers over N transmission lines in which an array of orthogonal RAM memory devices provide parallel-to-serial conversion and multiplexing of the N words each of M bit length to provide a time division multiplexed serial digital bit stream of M words, each N bits in length, which are transmitted over a transmission line to a serial-to-parallel converter and coupled to a second orthogonal RAM memory device in which the N words M bits in length from the serial-to-parallel converter are stored and coupled to N telephone data subscribers over the transmission lines.

Abstract: A digital switching system for switching messages between a plurality of subscribers located a relatively short distance from the switching system. The message format for the system comprises the serial transmission of messages of M bits of information which are transmitted from the switching system to the subscribers during one-half of a transmission frame and messages of M bits of information which are transmitted from the subscribers to the switching system during the other half of the transmission format. Addressable memory arrays are employed at the switching system for multiplexing and serial-to-parallel conversion and switching. In a preferred embodiment up to 40 telephone and/or data terminal messages are handled in 125 microsecond time frames with 8 bit voice and 8 bit data words plus a start and stop bit and 1 signalling bit message format from each of the subscribers.

Abstract: A two-wire bidirectional transmission system for transmitting electrical signals simultaneously in opposite directions between terminals over a pair of wires wherein the transmitter at one terminal transmits a voltage signal over one of said wires while the transmitter at the second terminal generates a voltage signal over the same wire, the second wire being grounded at each end. Impedance matching resistors, that is resistors matched to the impedance of the two wires, are coupled between each of the transmitters and the wire upon which the voltage signal is generated. A subtractor circuit is provided at each of the terminals for linearly subtracting a signal proportional to one-half of the voltage transmitted and thereby receiving at each terminal a voltage signal equal to one-half of the voltage transmitted by the opposite terminal.

Abstract: A low power line driving transmission apparatus is described in which TDM signals are transmitted between points over a transmission line comprising a pair of conductors and in which the characteristic impedance of the tranmission line and the source impedance of the transmitters is matched and wherein the input impedance of the receivers is sufficiently high to present an effective open circuit to received signals. Under these conditions the transmitter dissipates power only during logical transitions of the input signals.

Abstract: A pair of fixed capacitors are connected across a pair of serially coupled switched capacitors, the junction of the fixed capacitors being coupled to the floating node of the switched capacitors. As the polarities of the switched capacitors are switched, the fixed capacitors cause a partial discharge, thereby preventing charge from accumulating on the node.

Abstract: A comparator circuit of one type, prior to this invention, had a reliability problem due to an undesirable conductive path, and had limited speed due to stray capacitances. Reliability is achieved through separate triodes for coupling an inverted storage pulse to a primary electrode of each of two triodes of a differential amplifier. Speed is achieved through coupling a transistor across the other primary electrodes of the differential amplifier, the transistor's gate electrode receiving a narrow pulse upon termination of the storage pulse.

Abstract: Multiplexor with internal decoding. Signal levels at two select input terminals select the data input at one of four data input terminals to be applied to an output terminal. The multiplexor includes three sets of pairs of transistors connected in a series arrangement. In one embodiment the current source for the transistors includes a resistance and diode in parallel connected between ground and the transistors of the third set and a resistance connected between a source of negative potential and the transistors of the first set. In another embodiment the current source includes a dual emitter transistor biased to operate as a constant current source connected between the source of negative potential and the transistors of the first set in place of the resistance.

Abstract: Programmable logic arrays can be formed utilizing emitter coupled logic. Input terminals and control terminals associated with a programmable logic array module are coupled to the input terminals of a predetermined set of OR circuit means within the module. The outputs of the OR circuit means are coupled to various input terminals of a number of AND gates within the module. The outputs of the AND gates are coupled respectively to output terminals associated with the programmable logic array. The OR circuit means and the AND gates are coupled together in an emitter coupled logic format.

Abstract: Methods of and apparatus for generating precise reference voltages in a system utilizing a reference voltage V is disclosed including apparatus having a comparator, a voltage-to-current pulse converter having an input coupled to an output terminal of the comparator, a storage capacitor coupled across the output of the converter, and a point of reference potential, a buffer having an input coupled to the output of the converter, means for applying a reference voltage V to one terminal of a first capacitor while the second terminal of the first capacitor is coupled to a point of reference potential, means for decoupling the second terminal from the point of reference potential while the second terminal of the first capacitor remains coupled to an input terminal of a comparator, and means for applying the output of the buffer to a first terminal of the second capacitor wherein a second terminal of the second capacitor is coupled to the input terminal of the comparator.

Abstract: The output of a differential amplifier, operating as a comparator, is coupled through a first switch to charge a small valued capacitor C.sub.1. The charge in the small capacitor can be coupled through a second switch to charge a larger value capacitor C.sub.2. The charge on the larger capacitor creates a voltage thereacross which is C.sub.1 /(C.sub.1 +C.sub.2) that which was initially across capacitor C.sub.1. The voltage across the capacitor C.sub.2 is coupled to the negative terminal of the differential amplifier and is lessened in value via a buffer and attenuator circuit. The positive terminal is coupled to ground. The output of the comparator would normally have a polarity based upon the sign of the "offset error" of the comparator less the voltage at the negative terminal.