Patents by Inventor Michael Corwin

Michael Corwin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11414639
    Abstract: A bioreactor vessel includes a bottom plate, a vessel body coupled to the bottom plate, the vessel body and the bottom plate defining an interior compartment therebetween, and a plurality of recesses formed in the bottom plate, each recess of the plurality of recesses being configured to receive a corresponding alignment pin on a bed plate for aligning the bioreactor vessel on the bed plate.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: August 16, 2022
    Assignee: GLOBAL LIFE SCIENCES SOLUTIONS USA LLC
    Inventors: Weston Blaine Griffin, Alex D Corwin, Xiaohua Zhang, Reginald Donovan Smith, Zhen Liu, Chengkun Zhang, Vandana Keskar, Brian Michael Davis, Kashan Shaikh
  • Publication number: 20220251496
    Abstract: A bioprocessing system includes a first fluid assembly having a first fluid assembly line connected to a first port of a first bioreactor vessel though a first bioreactor line of a first bioreactor vessel, a second fluid assembly having a second fluid assembly line connected to a second port of the first bioreactor vessel through a second bioreactor line of the first bioreactor vessel, and an interconnect line providing for fluid communication between the first fluid assembly and the second fluid assembly, and for fluid communication between the second bioreactor line of the first bioreactor vessel and the first bioreactor line of the first bioreactor vessel.
    Type: Application
    Filed: May 2, 2022
    Publication date: August 11, 2022
    Applicant: Global Life Sciences Solutions USA LLC
    Inventors: Weston Blaine Griffin, Alex D. Corwin, Xiaohua Zhang, Reginald Donovan Smith, Zhen Liu, Chengkun Zhang, Vandana Keskar, Brian Michael Davis, Kashan Shaikh
  • Patent number: 11371007
    Abstract: A bioprocessing system includes a first fluid assembly having a first fluid assembly line connected to a first port of a first bioreactor vessel though a first bioreactor line of a first bioreactor vessel, a second fluid assembly having a second fluid assembly line connected to a second port of the first bioreactor vessel through a second bioreactor line of the first bioreactor vessel, and an interconnect line providing for fluid communication between the first fluid assembly and the second fluid assembly, and for fluid communication between the second bioreactor line of the first bioreactor vessel and the first bioreactor line of the first bioreactor vessel.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: June 28, 2022
    Assignee: GLOBAL LIFE SCIENCES SOLUTIONS USA LLC
    Inventors: Weston Blaine Griffin, Alex D Corwin, Xiaohua Zhang, Reginald Donovan Smith, Zhen Liu, Chengkun Zhang, Vandana Keskar, Brian Michael Davis, Kashan Shaikh
  • Patent number: 9378231
    Abstract: Embodiments of the present invention provide one or more hardware-friendly data structures that enable efficient hardware acceleration of database operations. In particular, the present invention employs a column-store format for the database. In the database, column-groups are stored with implicit row ids (RIDs) and a RID-to-primary key column having both column-store and row-store benefits via column hopping and a heap structure for adding new data. Fixed-width column compression allow for easy hardware database processing directly on the compressed data. A global database virtual address space is utilized that allows for arithmetic derivation of any physical address of the data regardless of its location. A word compression dictionary with token compare and sort index is also provided to allow for efficient hardware-based searching of text. A tuple reconstruction process is provided as well that allows hardware to reconstruct a row by stitching together data from multiple column groups.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: June 28, 2016
    Assignee: Teradata US, Inc.
    Inventors: Liuxi Yang, Kapil Surlaker, Ravi Krishnamurthy, Michael Corwin, Jeremy Branscome, Krishnan Meiyyappan, Joseph I. Chamdani
  • Patent number: 8862625
    Abstract: Embodiments of the present invention provide hardware-friendly indexing of databases. In particular, forward and reverse indexing are utilized to allow for easy traversal of primary key to foreign key relationships. A novel structure known as a hit list also allows for easy scanning of various indexes in hardware. Group indexing is provided for flexible support of complex group key definition, such as for date range indexing and text indexing. A Replicated Reordered Column (RRC) may also be added to the group index to convert random I/O pattern into sequential I/O of only needed column elements.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: October 14, 2014
    Assignee: Teradata US, Inc.
    Inventors: Krishnan Meiyyappan, Liuxi Yang, Jeremy Branscome, Michael Corwin, Ravi Krishnamurthy, Kapil Surlaker, James Shau, Joseph I. Chamdani
  • Patent number: 8244718
    Abstract: Embodiments of the present invention provide a database system that is optimized by using hardware acceleration. The system may be implemented in several variations to accommodate a wide range of queries and database sizes. In some embodiments, the system may comprise a host system that is coupled to one or more hardware accelerator components. The host system may execute software or provide an interface for receiving queries. The host system analyzes and parses these queries into tasks. The host system may then select some of the tasks and translate them into machine code instructions, which are executed by one or more hardware accelerator components. The tasks executed by hardware accelerators are generally those tasks that may be repetitive or processing intensive. Such tasks may include, for example, indexing, searching, sorting, table scanning, record filtering, and the like.
    Type: Grant
    Filed: August 27, 2007
    Date of Patent: August 14, 2012
    Assignee: Teradata US, Inc.
    Inventors: Joseph I. Chamdani, Raj Cherabuddi, Michael Corwin, Jeremy Branscome, Liuxi Yang, Ravi Krishnamurthy
  • Patent number: 8234267
    Abstract: Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCle or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: July 31, 2012
    Assignee: Teradata US, Inc.
    Inventors: Jeremy Branscome, Michael Corwin, Liuxi Yang, Joseph I. Chamdani
  • Patent number: 8229918
    Abstract: Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCle or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: July 24, 2012
    Assignee: Teradata US, Inc.
    Inventors: Jeremy Branscome, Michael Corwin, Liuxi Yang, Joseph I. Chamdani
  • Patent number: 8224800
    Abstract: Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCle or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: July 17, 2012
    Assignee: Teradata US, Inc.
    Inventors: Jeremy Branscome, Michael Corwin, Liuxi Yang, Joseph I. Chamdani
  • Publication number: 20110246432
    Abstract: Embodiments of the present invention provide one or more hardware-friendly data structures that enable efficient hardware acceleration of database operations. In particular, the present invention employs a column-store format for the database. In the database, column-groups are stored with implicit row ids (RIDs) and a RID-to-primary key column having both column-store and row-store benefits via column hopping and a heap structure for adding new data. Fixed-width column compression allow for easy hardware database processing directly on the compressed data. A global database virtual address space is utilized that allows for arithmetic derivation of any physical address of the data regardless of its location. A word compression dictionary with token compare and sort index is also provided to allow for efficient hardware-based searching of text. A tuple reconstruction process is provided as well that allows hardware to reconstruct a row by stitching together data from multiple column groups.
    Type: Application
    Filed: May 13, 2011
    Publication date: October 6, 2011
    Applicant: TERADATA US, INC.
    Inventors: Liuxi Yang, Kapil Surlaker, Ravi Krishnamurthy, Michael Corwin, Jeremy Branscome, Krishnan Meiyyappan, Joseph I. Chamdani
  • Publication number: 20110218987
    Abstract: Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCle or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested.
    Type: Application
    Filed: March 15, 2011
    Publication date: September 8, 2011
    Applicant: TERADATA US, INC.
    Inventors: JEREMY BRANSCOME, MICHAEL CORWIN, LIUXI YANG, JOSEPH I. CHAMDANI
  • Publication number: 20110167083
    Abstract: Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCle or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested.
    Type: Application
    Filed: March 15, 2011
    Publication date: July 7, 2011
    Applicant: TERADATA US, INC.
    Inventors: JEREMY BRANSCOME, MICHAEL CORWIN, LIUXI YANG, JOSEPH I. CHAMDANI
  • Publication number: 20110167055
    Abstract: Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCle or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested.
    Type: Application
    Filed: March 15, 2011
    Publication date: July 7, 2011
    Applicant: TERADATA US, INC.
    Inventors: JEREMY BRANSCOME, MICHAEL CORWIN, LIUXI YANG, JOSEPH I. CHAMDANI
  • Patent number: 7966343
    Abstract: Embodiments of the present invention provide one or more hardware-friendly data structures that enable efficient hardware acceleration of database operations. In particular, the present invention employs a column-store format for the database. In the database, column-groups are stored with implicit row ids (RIDs) and a RID-to-primary key column having both column-store and row-store benefits via column hopping and a heap structure for adding new data. Fixed-width column compression allow for easy hardware database processing directly on the compressed data. A global database virtual address space is utilized that allows for arithmetic derivation of any physical address of the data regardless of its location. A word compression dictionary with token compare and sort index is also provided to allow for efficient hardware-based searching of text. A tuple reconstruction process is provided as well that allows hardware to reconstruct a row by stitching together data from multiple column groups.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: June 21, 2011
    Assignee: Teradata US, Inc.
    Inventors: Liuxi Yang, Kapil Surlaker, Ravi Krishnamurthy, Michael Corwin, Jeremy Branscome, Krishnan Meiyyappan, Joseph I. Chamdani
  • Patent number: 7952997
    Abstract: A scalable solution to managing congestion in a network is disclosed. In one implementation, such a solution comprises a means for managing traffic including at least one flow monitor and a plurality of flow control regulators that together manage congestion within a network. Each of the flow control regulators monitor traffic at a corresponding ingress point and determine a state of the ingress point corresponding to the traffic monitored at the ingress point. Each flow control regulators forward the state (or information representative of the state) to the flow monitor. The flow monitor detects congestion based upon the states of the flow control regulators and, in the event of congestion, determines a target bandwidth for the ingress points. The flow monitor provides a control signal to at least one of the flow control regulators, and at least one of the flow control regulators control flows at its corresponding ingress point based upon the control signal received from the flow monitor.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: May 31, 2011
    Assignee: MCDATA Corporation
    Inventors: Michael Corwin, Joseph Chamdani, Stephen Trevitt
  • Patent number: 7908259
    Abstract: Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCIe or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested.
    Type: Grant
    Filed: August 27, 2007
    Date of Patent: March 15, 2011
    Assignee: Teradata US, Inc.
    Inventors: Jeremy Branscome, Michael Corwin, Liuxi Yang, Joseph I. Chamdani
  • Publication number: 20100082895
    Abstract: A multi-level content addressable memory (CAM) architecture compresses out much of the redundancy encountered in the search space of a single CAM, particularly for flow-based lookups in a network. Destination and source address may be associated with internal equivalence classes independently in one level of the multi-level CAM architecture, while flow-specific properties linking arbitrary classes of the destination and source addresses may be applied in a later level of the multi-level CAM.
    Type: Application
    Filed: September 25, 2009
    Publication date: April 1, 2010
    Inventors: Jeremy Branscome, Michael Corwin
  • Publication number: 20100005077
    Abstract: Embodiments of the present invention generate and optimize query plans that are at least partially executable in hardware. Upon receiving a query, the query is rewritten and optimized with a bias for hardware execution of fragments of the query. A template-based algorithm may be employed for transforming a query into fragments and then into query tasks. The various query tasks can then be routed to either a hardware accelerator, a software module, or sent back to a database management system for execution. For those tasks routed to the hardware accelerator, the query tasks are compiled into machine code database instructions.
    Type: Application
    Filed: July 7, 2008
    Publication date: January 7, 2010
    Applicant: Kickfire, Inc.
    Inventors: Ravi Krishnamurthy, Chi-Young Ku, James Shau, Chun Zhang, Kapil Surlaker, Jeremy Branscome, Michael Corwin, Joseph I. Chamdani
  • Patent number: 7606968
    Abstract: A multi-level content addressable memory (CAM) architecture compresses out much of the redundancy encountered in the search space of a single CAM, particularly for flow-based lookups in a network. Destination and source address may be associated with internal equivalence classes independently in one level of the multi-level CAM architecture, while flow-specific properties linking arbitrary classes of the destination and source addresses may be applied in a later level of the multi-level CAM.
    Type: Grant
    Filed: May 8, 2006
    Date of Patent: October 20, 2009
    Assignee: McData Corporation
    Inventors: Jeremy Branscome, Michael Corwin
  • Publication number: 20090254516
    Abstract: Embodiments of the present invention provide hardware-friendly indexing of databases. In particular, forward and reverse indexing are utilized to allow for easy traversal of primary key to foreign key relationships. A novel structure known as a hit list also allows for easy scanning of various indexes in hardware. Group indexing is provided for flexible support of complex group key definition, such as for date range indexing and text indexing. A Replicated Reordered Column (RRC) may also be added to the group index to convert random I/O pattern into sequential I/O of only needed column elements.
    Type: Application
    Filed: April 7, 2008
    Publication date: October 8, 2009
    Inventors: Krishnan Meiyyappan, Liuxi Yang, Jeremy Branscome, Michael Corwin, Ravi Krishnamurthy, Kapil Surlaker, James Shau, Joseph I. Chamdani