Abstract: Embodiments of the present invention provide one or more hardware-friendly data structures that enable efficient hardware acceleration of database operations. In particular, the present invention employs a column-store format for the database. In the database, column-groups are stored with implicit row ids (RIDs) and a RID-to-primary key column having both column-store and row-store benefits via column hopping and a heap structure for adding new data. Fixed-width column compression allow for easy hardware database processing directly on the compressed data. A global database virtual address space is utilized that allows for arithmetic derivation of any physical address of the data regardless of its location. A word compression dictionary with token compare and sort index is also provided to allow for efficient hardware-based searching of text. A tuple reconstruction process is provided as well that allows hardware to reconstruct a row by stitching together data from multiple column groups.

Abstract: The present invention comprises a dual-use form factor for rack mounting equipment. In particular, the form-factor is configured so that it can be both rack-mounted directly or installed within a chassis. In addition, the form-factor may comprise one or more blind-mate connector systems that are suitable for blunt-type connectors, such as PCIe connectors.

Abstract: Flexible virtual queues of a switch are allocated to provide non-blocking virtual output queue (VOQ) support. A port ASIC has a set of VOQs, one VOQ per supported port of the switch. For each VOQ, a set of virtual input queues (VIQs) includes a VIQ for each input port of the port ASIC that forms a non-blocking flow with the corresponding output port (and potentially, with the specified level of service) in the switch. The port ASIC selects a VOQ for transmission and then arbitrates among the VIQs of the selected VOQ to select a VIQ from which to transmit the packet. Having identified an appropriate VIQ, the port ASIC transmits cells of the packet at the head of the VIQ to a port ASIC that includes the corresponding output port for reassemble and eventual transmission through the output port.

Abstract: Embodiments of the present invention provide processing elements that are capable of performing high level database operations in hardware based on machine code instructions. These processing elements employ a dataflow architecture that operates on data in hardware without interruption or software. A scanning/indexing processing element may comprise logic that analyze database column groups stored in local memory, perform parallel field extraction and comparison, and generates a list of row pointers (row ids or RIDs) referencing those rows whose value(s) satisfy an applied predicate. The scanning/indexing processing may also be used to project database column groups, search and join index structures, and manipulate in-flight metadata flows, composing, merging, reducing, and modifying multi-dimensional lists of intermediate and final results.

Abstract: Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCIe or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested.

Abstract: Embodiments of the present invention provide a database system that is optimized by using hardware acceleration. The system may be implemented in several variations to accommodate a wide range of queries and database sizes. In some embodiments, the system may comprise a host system that is coupled to one or more hardware accelerator components. The host system may execute software or provide an interface for receiving queries. The host system analyzes and parses these queries into tasks. The host system may then select some of the tasks and translate them into machine code instructions, which are executed by one or more hardware accelerator components. The tasks executed by hardware accelerators are generally those tasks that may be repetitive or processing intensive. Such tasks may include, for example, indexing, searching, sorting, table scanning, record filtering, and the like.

Abstract: A scalable solution to managing fairness in a congested hierarchical switched system is disclosed. The solution comprises a means for managing fairness during congestion in a hierarchical switched system comprising a first level arbitration system and a second level arbitration system of a stage. The first level arbitration system comprises a plurality of arbitration segments that arbitrate between information flows received from at least one ingress point based upon weights associated with those information flows (or the ingress points). Each arbitration segment determines an aggregate weight from each active ingress point providing the information flows to the segment and forwards a selected information flow along with the aggregate weight (in-band or out-of-band) to the second level arbitration system.

Abstract: A scalable solution to managing congestion in a network is disclosed. In one implementation, such a solution comprises a means for managing traffic including at least one flow monitor and a plurality of flow control regulators that together manage congestion within a network. Each of the flow control regulators monitor traffic at a corresponding ingress point and determine a state of the ingress point corresponding to the traffic monitored at the ingress point. Each flow control regulators forward the state (or information representative of the state) to the flow monitor. The flow monitor detects congestion based upon the states of the flow control regulators and, in the event of congestion, determines a target bandwidth for the ingress points. The flow monitor provides a control signal to at least one of the flow control regulators, and at least one of the flow control regulators control flows at its corresponding ingress point based upon the control signal received from the flow monitor.

Abstract: A method, system or switch device, the switch device being one of a ported and a non-ported switch device, both including a housing containing an ASIC providing a switching system within the switch device; the housing further including a plurality of extender ports communicating with the ASIC and being connectable to themselves either in loopback fashion or to one or more ported or non-ported switch devices, whereby the extender ports operate on a discrete protocol from standard switch ports. The ported switch device further includes a plurality of standard ports connectable to one or more external computer network devices and is adapted to be operable as a switch system in an independent standalone mode as well as being adapted to be operable in conjunction with a discrete non-ported switch device.

Abstract: A multi-level content addressable memory (CAM) architecture compresses out much of the redundancy encountered in the search space of a single CAM, particularly for flow-based lookups in a network. Destination and source address may be associated with internal equivalence classes independently in one level of the multi-level CAM architecture, while flow-specific properties linking arbitrary classes of the destination and source addresses may be applied in a later level of the multi-level CAM.

Abstract: A method, system or switch device, the switch device being one of a ported and a non-ported switch device, either of which including a housing containing an ASIC providing a switching system within the switch device, the housing further including a plurality of extender ports communicating with the ASIC and being connectable to themselves either in loopback fashion or to one or more ported or non-ported switch devices, whereby the extender ports operate on a discrete protocol from standard switch ports. The ported switch device further includes a plurality of standard ports connectable to one or more external computer network devices. A switch device hereof is adapted to send and/or receive an identification communication, the identification communication adapted to be indicative of the health of a switch device or a connecting link in a switch system.

Abstract: A switching device comprises at least two base racks, each base rack including a switch card in communication with a line card across a backplane, the line card having at least an external port. The at least two base racks are coupled such that the switch cards of each are linked. A method for switching a packet comprises introducing the packet into an external port on a first base rack, transmitting the packet from a first cascade port on the first base rack to a second cascade port on a second base rack, and sending the packet out of the second base rack through a second external port.

Abstract: A device for ensuring reliable data packet throughput in a redundant system includes a splitter that creates copies of a data packet and sends each copy to a separate intermediate source for processing, parallel buffers for receiving the processed packets from the intermediate sources, and a comparator for determining whether the data packets are equivalent.

Abstract: A non-volatile, anti-gel compound having a chain of at least about 5 repeat units of an alkylene oxide and which is soluble in olefin polymers, and an inorganic anti-block agent having a substantially neutral pH are added to a film grade transition metal catalyzed resin containing halide residues such as Ziegler-Natta catalyzed olefin polymer compositions to prevent: (1) gel streaking/pinstriping during film extrusion processes; (2) blocking of the extruded film; and (3) discoloration of the extruded film upon aging. The anti-gel compound has a molecular weight between about 200 and about 4,000,000 Daltons.

Abstract: A non-volatile, anti-gel compound having a chain of at least about 5 repeat units of an alkylene oxide and which is soluble in olefin polymers, and an inorganic anti-block agent having a substantially neutral pH are added to a film grade transition metal catalyzed resin containing halide residues such as Ziegler-Natta catalyzed olefin polymer compositions to prevent: (1) gel streaking/pinstriping during film extrusion processes; (2) blocking of the extruded film; and (3) discoloration of the extruded film upon aging. The anti-gel compound has a molecular weight between about 200 and about 4,000,000 Daltons.