Abstract: Systems and methods described herein are related to clock signal generation for synchronous electronic circuitry. Power management in electronic devices circuitry may be implemented by scaling the frequency multiple functional modules implemented in the synchronous electronic circuitry. The present disclosure discussed clock generators that may provide frequency scaling of clock signals for functional modules within an electronic device. Moreover, certain clock signal generators may reduce mitigate generation of large currents during frequency scaling by employing circuitry that leads to incremental frequency changes. Circuitry that allows substantially glitchless or reduced-glitch transition between clock rate frequencies are also discussed.

Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.

Abstract: Systems and methods described herein are related to clock signal generation for synchronous electronic circuitry. Power management in electronic devices circuitry may be implemented by scaling the frequency multiple functional modules implemented in the synchronous electronic circuitry. The present disclosure discussed clock generators that may provide frequency scaling of clock signals for functional modules within an electronic device. Moreover, certain clock signal generators may reduce mitigate generation of large currents during frequency scaling by employing circuitry that leads to incremental frequency changes. Circuitry that allows substantially glitchless or reduced-glitch transition between clock rate frequencies are also discussed.

Abstract: Systems and methods described herein are related to clock signal generation for synchronous electronic circuitry. Power management in electronic devices circuitry may be implemented by scaling the frequency multiple functional modules implemented in the synchronous electronic circuitry. The present disclosure discussed clock generators that may provide frequency scaling of clock signals for functional modules within an electronic device. Moreover, certain clock signal generators may reduce mitigate generation of large currents during frequency scaling by employing circuitry that leads to incremental frequency changes. Circuitry that allows substantially glitchless or reduced-glitch transition between clock rate frequencies are also discussed.

Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.

Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.

Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.

Abstract: Systems and methods described herein are related to clock signal generation for synchronous electronic circuitry. Power management in electronic devices circuitry may be implemented by scaling the frequency multiple functional modules implemented in the synchronous electronic circuitry. The present disclosure discussed clock generators that may provide frequency scaling of clock signals for functional modules within an electronic device. Moreover, certain clock signal generators may reduce mitigate generation of large currents during frequency scaling by employing circuitry that leads to incremental frequency changes. Circuitry that allows substantially glitchless or reduced-glitch transition between clock rate frequencies are also discussed.

Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.

Abstract: An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, a processing circuit, and a configurable control circuit. The configurable storage block may receive an instruction which may be decoded in the control block to identify a command. The command may be associated with a pre-defined sequence of operations that the control block executes by directing the memory array to perform memory access operations and the processing circuit to execute data processing operations. These data processing operations may be executed on data retrieved during memory access operations, data received subsequent to receiving the instruction, or previously computed data. The processed data may be provided for further processing outside the configurable storage block or stored in the memory array. The configurable storage block may further have delay blocks to allow for delayed memory access to the memory array.

Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.

Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.

Abstract: A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

Abstract: Integrated circuits such as application specific integrated circuits or programmable logic devices may include sequential elements such as configurable register circuitry. Such configurable register circuitry may operate as independent registers controlled by selectable clock signals or as a single register with error detection and error correction capabilities. For example, the configurable register circuitry when operated as single register with error detection and error correction circuitry may detect and correct runtime errors caused by manufacturing and environmental variations, thereby allowing an increase in the clock rate that controls the register. If desired, the configurable register circuitry may be configured to detect single event upsets, which may enable the implementation of safe finite state machines.

Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.

Abstract: A hybrid programmable logic is described that performs packet processing functions on received data packets using programmable logic elements, and processors interleaved with the programmable logic elements. The header data may be scheduled for distribution to processing threads associated with the processors by the programmable logic elements. The processors may perform packet processing functions on the header data using both the processing threads and hardware acceleration functions provided by the programmable logic elements.

Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.

Abstract: A packaged component may include an interposer and integrated circuit dies mounted on the interposer. At least one of the dies may be a radiation-hardened integrated circuit die, whereas the remaining dies may be non-radiation-hardened dies. If desired, the interposer may be a radiation-hardened interposer whereas the integrated circuit dies may be non-radiation-hardened dies. The radiation-hardened die or the radiation-hardened interposer may include monitor circuitry that is used to test non-radiation-hardened circuitry of the packaged component. Test results may be stored in a database at the monitor circuitry or transmitted to external devices such as a server. The monitor circuitry may be used to reconfigure failed circuitry or may control multiplexing circuitry in the interposer to functionally replace the failed circuitry. If desired, the monitor circuitry may adjust power consumption of non-radiation-hardened circuitry based on the test results.

Abstract: Hybrid adder circuitry is provided for integrated circuits such as programmable integrated circuits. The hybrid adder may combine the capabilities of multiple adder architectures. Hybrid adders may include carry select and carry ripple adder circuits. The adder circuits may be combined using a carry look-ahead architecture. Adder functionality may be implemented using the resources of logic regions on the programmable integrated circuits. Each logic region may include combinatorial logic such as look-up table logic and register circuitry. The hybrid adder circuitry may receive input words to be added from the combinatorial circuitry and may produce corresponding arithmetic sum output signals to the register circuitry.

Abstract: A packaged component may include an interposer and integrated circuit dies mounted on the interposer. At least one of the dies may be a radiation-hardened integrated circuit die, whereas the remaining dies may be non-radiation-hardened dies. If desired, the interposer may be a radiation-hardened interposer whereas the integrated circuit dies may be non-radiation-hardened dies. The radiation-hardened die or the radiation-hardened interposer may include monitor circuitry that is used to test non-radiation-hardened circuitry of the packaged component. Test results may be stored in a database at the monitor circuitry or transmitted to external devices such as a server. The monitor circuitry may be used to reconfigure failed circuitry or may control multiplexing circuitry in the interposer to functionally replace the failed circuitry. If desired, the monitor circuitry may adjust power consumption of non-radiation-hardened circuitry based on the test results.