Abstract: A circuit designer may use computer-aided design (CAD) tools to implement an integrated circuit design. The CAD tools may include auto-pipelining capabilities to improve the performance of the integrated circuit design. Auto-pipelining may modify the number of pipeline registers in a path within a given range. A description of the integrated circuit design may include different implementation alternatives of a path each having a different number of pipeline registers, and the CAD tools may select one of these implementation alternatives. The CAD tools may further evaluate the performance of a particular implementation alternative and iteratively select a different implementation alternative until a given objective is met. The CAD tool may update a test environment according to the selected implementation alternative once the objective is met and validate the selected implementation alternative using the updated test environment.

Abstract: An integrated circuit may have configurable storage blocks. Multiple configurable storage blocks may share one or more internal address busses with selected configurable storage blocks having access a given address bus. An address bus may be unidirectional or bidirectional and may convey the same address signal from one configurable address block to another or to several other configurable storage blocks. Tri-state buffers or multiplexers may selectively couple or decouple the address bus between configurable storage blocks. Redundant address bus paths may bypass configurable address blocks in neighboring rows or columns allowing for disabling the respective row or column. The address bus may further have pipeline registers to allow for pipelined access to configurable storage blocks.

Abstract: A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.

Abstract: Integrated circuits may include logic regions configurable to perform custom functions. Interconnects may be used to rout signals throughout the integrated circuit. The logic region may be coupled to input selection circuitry for selecting and providing input signals from the interconnects to the logic regions and to output selection and routing circuitry for selecting and transmitting output signals over interconnects to other logic regions. Bypass circuitry may provide direct access to registers inside the logic regions and to the output selection and routing circuitry by bypassing the input selection circuitry and other processing circuitry inside the logic regions. Bus interconnections having logic regions performing register pipelining, wire stitching, and acting as data source/sink stations to get on and off the bus interconnections may be generated by configuring the bypass circuitry and the output selection and routing circuitry appropriately.

Abstract: An integrated circuit (IC) includes a substrate that is common to the IC and variants of the IC. The IC also includes a first set of interconnect layers fabricated above the substrate. The first set of interconnect layers is used to couple programmable interconnect of the IC to a first circuit in the substrate. The IC further includes a second set of interconnect layers fabricated above the substrate. The second set of interconnect layers is used to differentiate features of the IC from variants of the IC by selectively coupling the programmable interconnect to a second circuit in the substrate.

Abstract: An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.

Abstract: A circuit designer may use computer-aided design (CAD) tools to implement an integrated circuit design. The CAD tools may include auto-pipelining capabilities to improve the performance of the integrated circuit design. Auto-pipelining may modify the number of pipeline registers in a path within a given range. A description of the integrated circuit design may include different implementation alternatives of a path each having a different number of pipeline registers, and the CAD tools may select one of these implementation alternatives. The CAD tools may further evaluate the performance of a particular implementation alternative and iteratively select a different implementation alternative until a given objective is met. The CAD tool may update a test environment according to the selected implementation alternative once the objective is met and validate the selected implementation alternative using the updated test environment.

Abstract: A skew generator unit includes a delay chain. The delay chain is coupled to a clock line that transmits a clock signal. The delay chain generates a skewed clock signal having a unit of delay from the clock signal. The skew generator unit also includes a selector. The selector is coupled to the delay chain and the clock line and may select one of the clock signal and the skewed clock signal.

Abstract: A packaged component may include an interposer and integrated circuit dies mounted on the interposer. At least one of the dies may be a radiation-hardened integrated circuit die, whereas the remaining dies may be non-radiation-hardened dies. If desired, the interposer may be a radiation-hardened interposer whereas the integrated circuit dies may be non-radiation-hardened dies. The radiation-hardened die or the radiation-hardened interposer may include monitor circuitry that is used to test non-radiation-hardened circuitry of the packaged component. Test results may be stored in a database at the monitor circuitry or transmitted to external devices such as a server. The monitor circuitry may be used to reconfigure failed circuitry or may control multiplexing circuitry in the interposer to functionally replace the failed circuitry. If desired, the monitor circuitry may adjust power consumption of non-radiation-hardened circuitry based on the test results.

Abstract: Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom functions. Interconnects may be used to route signals throughout the integrated circuit. The programmable logic regions may have input selection circuitry for selecting and providing input signals from the interconnects to the programmable logic regions. The programmable logic regions may include look-up table circuitry for processing the input signals and registers for storing output signals from the look-up table circuitry. The programmable logic regions may include output selection circuitry for selecting which output signals are provided to output circuitry of the programmable logic regions. The programmable logic regions may include bypass paths that provide direct access to the registers from the interconnects by bypassing the input and output selection circuitry.

Abstract: Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom user functions. The programmable logic regions may produce output signals. The integrated circuit may include interconnects that route selected output signals throughout the integrated circuit. The integrated circuit may include output selection circuitry having output selection and interconnect selection stages. The output selection circuitry may be configured to select which of the output signals produced by the programmable logic regions are provided to the interconnects for routing. The interconnect selection stage may be formed using multiplexing circuits or tristate drivers. Logic design system computing equipment may be used to generate configuration data that can be used to program the output selection circuitry to reduce crosstalk by routing signals away from critical interconnects or by double-driving critical interconnects.

Abstract: An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.

Abstract: Integrated circuits may include logic regions configurable to perform custom functions. Interconnects may be used to route signals throughout the integrated circuit. The logic region may be coupled to input selection circuitry for selecting and providing input signals from the interconnects to the logic regions and to output selection and routing circuitry for selecting and transmitting output signals over interconnects to other logic regions. Bypass circuitry may provide direct access to registers inside the logic regions and to the output selection and routing circuitry by bypassing the input selection circuitry and other processing circuitry inside the logic regions. Bus interconnections having logic regions performing register pipelining, wire stitching, and acting as data source/sink stations to get on and off the bus interconnections may be generated by configuring the bypass circuitry and the output selection and routing circuitry appropriately.

Abstract: A skew generator unit includes a delay chain. The delay chain is coupled to a clock line that transmits a clock signal. The delay chain generates a skewed clock signal having a unit of delay from the clock signal. The skew generator unit also includes a selector. The selector is coupled to the delay chain and the clock line and may select one of the clock signal and the skewed clock signal.

Abstract: Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom functions. Interconnects may be used to route signals throughout the integrated circuit. The programmable logic regions may have input selection circuitry for selecting and providing input signals from the interconnects to the programmable logic regions. The programmable logic regions may include look-up table circuitry for processing the input signals and registers for storing output signals from the look-up table circuitry. The programmable logic regions may include output selection circuitry for selecting which output signals are provided to output circuitry of the programmable logic regions. The programmable logic regions may include bypass paths that provide direct access to the registers from the interconnects by bypassing the input and output selection circuitry.

Abstract: A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.

Abstract: Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom user functions. The programmable logic regions may produce output signals. The integrated circuit may include interconnects that route selected output signals throughout the integrated circuit. The integrated circuit may include output selection circuitry having output selection and interconnect selection stages. The output selection circuitry may be configured to select which of the output signals produced by the programmable logic regions are provided to the interconnects for routing. The interconnect selection stage may be formed using multiplexing circuits or tristate drivers. Logic design system computing equipment may be used to generate configuration data that can be used to program the output selection circuitry to reduce crosstalk by routing signals away from critical interconnects or by double-driving critical interconnects.

Abstract: Hybrid adder circuitry is provided for integrated circuits such as programmable integrated circuits. The hybrid adder may combine the capabilities of multiple adder architectures. Hybrid adders may include carry select and carry ripple adder circuits. The adder circuits may be combined using a carry look-ahead architecture. Adder functionality may be implemented using the resources of logic regions on the programmable integrated circuits. Each logic region may include combinatorial logic such as look-up table logic and register circuitry. The hybrid adder circuitry may receive input words to be added from the combinatorial circuitry and may produce corresponding arithmetic sum output signals to the register circuitry.

Abstract: An integrated circuit may include programmable logic regions coupled in parallel to an interconnect bus. Multiplexing circuitry may be interposed between the programmable logic regions and the interconnect bus. The multiplexing circuitry may be formed from multiplexing circuits formed in a cascade structure. The multiplexing circuitry may dynamically receive control signals that determines which programmable logic region is allowed to drive output signals onto the interconnect bus. Alternatively, each programmable logic region may have an associated output circuit that is coupled to the interconnect bus. The output circuits may be dynamically controlled by control circuitry. The output circuits may receive control signals from the control circuitry that selectively enable and selectively disable the output circuits. The output circuits may be formed with logic circuitry that ensures that the interconnect bus is not simultaneously driven by the output circuits.

Abstract: An integrated circuit may include programmable logic regions coupled in parallel to an interconnect bus. Multiplexing circuitry may be interposed between the programmable logic regions and the interconnect bus. The multiplexing circuitry may be formed from multiplexing circuits formed in a cascade structure. The multiplexing circuitry may dynamically receive control signals that determines which programmable logic region is allowed to drive output signals onto the interconnect bus. Alternatively, each programmable logic region may have an associated output circuit that is coupled to the interconnect bus. The output circuits may be dynamically controlled by control circuitry. The output circuits may receive control signals from the control circuitry that selectively enable and selectively disable the output circuits. The output circuits may be formed with logic circuitry that ensures that the interconnect bus is not simultaneously driven by the output circuits.