Abstract: Computing device expansion modules and control of their operation based on temperature are disclosed. According to an aspect, an expansion module includes an interface configured to operably connect to a computing device including a service manager. Further, the expansion module includes a controller configured to determine whether communication with the service manager of the computing device is enabled or not enabled. The controller is also configured to set a first temperature level at which operation of the expansion module is reduced in response to determining that communication with the service manager is enabled. Further, the controller is configured to set a second temperature level at which operation of the expansion module is reduced in response to determining that communication with the service manager is not enabled. The second temperature level is lower than the first temperature level.

Abstract: Computing device expansion modules and control of their operation based on temperature are disclosed. According to an aspect, an expansion module includes an interface configured to operably connect to a computing device including a service manager. Further, the expansion module includes a controller configured to determine whether communication with the service manager of the computing device is enabled or not enabled. The controller is also configured to set a first temperature level at which operation of the expansion module is reduced in response to determining that communication with the service manager is enabled. Further, the controller is configured to set a second temperature level at which operation of the expansion module is reduced in response to determining that communication with the service manager is not enabled. The second temperature level is lower than the first temperature level.

Abstract: A method of determining power fault information using a voltage regulator-down (VRD) device having a fault-pin output. The method may include receiving a fault indication from one of a plurality of fault detection devices, correlating the received fault indication with a timing signal having a predetermined time duration, applying a voltage change on the fault-pin output of the VRD device for the predetermined time duration corresponding to the timing signal, and applying the voltage change on the fault-pin output to a plurality of fuses. Based on the predetermined time duration associated with the applied voltage change, the plurality of fuses may be blown according to a binary pattern indicative of a fault type associated with the fault indication.

Abstract: Aspects of the present invention disclose a DIMM extraction tool for extracting a DIMM from a DIMM socket. Exemplary embodiments of the DIMM extraction tool include a frame adapted for use as an air baffle within the DIMM socket, a first arm and a second arm pivotably connected to the frame. When the first arm and second arm are in a resting position, the first and second arm respectively engage a first resting detent and a second resting detent to prevent pivotable rotation of the first arm and second arm in exemplary embodiments of the DIMM extraction tool. When the first arm and second arm are in a working position, the first arm and second arm respectively are adapted to releasably engage the DIMM and bias resilient latching arm of the DIMM socket.

Abstract: Systems and methods for determining an operational condition of a capacitor package are disclosed. According to an aspect, a system may include a capacitor package including a dielectric material operatively connected between a first terminal and a second terminal. The system may include a Zener diode being operatively connected with its cathode at a third terminal and its anode at the second terminal. The system may also include a test pin being conductively connected to the third terminal. The system may also include a testing module configured to receive an electrical output from the test pin. The testing module may also be configured to determine an operational condition of the capacitor package based on the electrical output. The testing module may further be configured to present the operational condition of the capacitor package.

Abstract: A method includes identifying a plurality of power supplies connected for supplying power to a computer system, wherein the plurality of power supplies includes at least one redundant power supply in a standby mode. For each of the plurality of power supplies identified, the method determines a length of a power supply cable connected between the power supply and a power distribution unit for supplying power to the power supply. The method further includes placing one or more of the plurality of power supplies in an active mode in ascending order of the length of the cable connected to the power supply, and supplying power to the computer system using the one or more of the plurality of power supplies in the active mode.

Abstract: Controlling power consumption of a voltage regulator in a computer system that includes computer memory and the voltage regulator is configured to provide regulated source voltage to the computer memory includes: receiving, by a voltage regulator controller, memory margin statistics of the computer memory, the memory margin statistics including data describing operational tolerance of the computer memory to source voltage signal variations; and adjusting, by the voltage regulator controller, one or more operating characteristics of the voltage regulator in dependence upon the memory margin statistics.

Abstract: Optimizing an I2C bus frequency, the bus including signal lines coupling a master and slave nodes, a signal line coupled to a rise time detection circuit monitoring a voltage of the signal line, the voltage alternating between a logic low and logic high, where optimizing the frequency includes: detecting, during a rise in the signal line, a first voltage, the first voltage being greater than the logic low voltage; starting a counter to increment once for each clock period of the circuit; detecting a second voltage on the signal line, the second voltage greater than the first and less than the logic high; stopping the counter; calculating, in dependence upon the clock period and the counter value, a rise time; determining whether the rise time is greater than a maximum threshold; and increasing the I2C bus frequency if the calculated rise time is greater than the maximum threshold.

Abstract: A method includes performing operations on a compute node including a plurality of processors each having a local PCI processing element and a local processor interconnect, wherein the local processor interconnect of each processor is connected to the local processor interconnect of at least one other processor. The method further includes identifying a PCI device that is directly attached to the local PCI processing element of a first one of the processors and positioned in an upstream airflow direction from the first processor. The operating system monitors the PCI device and, in response to determining that the PCI device is performing a power-intensive operation, directs operations away from the first processor to a second one of the processors, wherein the local processor interconnect of the second processor is directly connected to the processor interconnect of the first processor.

Abstract: A method for securing a serial bus shared by a control module and one or more subordinate electronic devices, the serial bus having a protocol specifying that messages on the serial bus have a source address and a destination address. The method comprises examining, by one or more processors of the control module, each message appearing on the serial bus that was not originated by the control module; identifying, by one or more processors of the control module, a suspect message that satisfies one or more suspect message criteria. The method includes updating, by one or more processors of the control module, an event metric, and testing to determine whether a threshold has been exceeded; and in the event the threshold has not been exceeded, initiating, by one or more processors of the control module, a co-transmission sufficient to disrupt consumption of the suspect message by a subordinate device.

Abstract: The present disclosure provides signaling control among multiple communication interfaces of an electronic device based on signal priority. According to an aspect, an electronic device includes multiple communication interfaces. The electronic device also includes a communication controller configured to determine priority of signals to be communicated on different communication interfaces among the plurality of communication interfaces. Further, the communication controller is configured to determine an order of communication of the signals among the different communication interfaces based on the priority of the signals to be communicated. The communication controller is also configured to control communication of the signals among the different communication interfaces based on the determined order of communication.

Abstract: An electronic system comprises: a pin sensor; and an integrated management module, wherein the integrated management module: identifies a location of a damaged connector between a semiconductor chip and a hardware socket, wherein the location of the damaged connector is described by one or more readings from the pin sensor, and wherein the damaged connector prevents a particular signal from being supplied to the semiconductor chip via the hardware socket; identifies the particular signal as an input for a particular semiconductor function; determines whether the semiconductor chip provides the particular semiconductor function; and adjusts a use of the semiconductor chip based on whether or not the semiconductor chip uses the particular signal to provide the particular semiconductor function.

Abstract: A computer program product includes a computer readable storage medium having program instructions embodied therewith, wherein the program instructions are executable by a processor to cause the processor to perform a method. The method comprises obtaining an activity level for each of a plurality of functions of an integrated circuit, wherein each function has a different physical location on the integrated circuit. The method further includes dynamically adjusting an amount of current supplied to the integrated circuit by each of a plurality of power stages of a DC voltage regulator to meet the current requirements of the plurality of functions and to control power losses between the power stages and the functions, wherein each power stage has a different physical location along a perimeter of the integrated circuit.

Abstract: A method includes identifying a plurality of power supplies connected for supplying power to a computer system, wherein the plurality of power supplies includes at least one redundant power supply in a standby mode. For each of the plurality of power supplies identified, the method determines a length of a power supply cable connected between the power supply and a power distribution unit for supplying power to the power supply. The method further includes placing one or more of the plurality of power supplies in an active mode in ascending order of the length of the cable connected to the power supply, and supplying power to the computer system using the one or more of the plurality of power supplies in the active mode.

Abstract: Embodiments of the invention provide a method, system and computer program product for dynamically locating a device within a data center. A method for dynamically locating a device within a data center includes wirelessly receiving in a fixed device amongst a multiplicity of devices in a data center, a request from a mobile device to locate a target device amongst the devices. The method also includes broadcasting a request to the multiplicity of devices to establish respective wireless identifiers based upon a proximity of each of the multiplicity of the devices to the target device relative to adjacent ones of the devices. The method yet further includes establishing a wireless identifier for the fixed device based upon a wireless identifier of an adjacent one of the devices. Finally, the method includes returning to the mobile device by the fixed device the established wireless identifier for the fixed device.

Abstract: Optimizing computer hardware usage in a computing system that includes a plurality of populated central processing unit (‘CPU’) sockets, including: determining, by a socket configuration module, a number of CPUs to be utilized during operation of the computing system; determining, by the socket configuration module, performance characteristics associated with each available CPU, the performance characteristics associated with each available CPU including information describing computing devices such as memory devices, input/output (‘I/O) devices, and other downstream devices that are coupled to one or more of the available CPUs; and selecting, by the socket configuration module in dependence upon the performance characteristics associated with each available CPU and a predetermined performance policy, a target CPU to utilize as a boot CPU.

Abstract: Optimizing computer hardware usage in a computing system that includes a plurality of populated central processing unit (‘CPU’) sockets, including: determining, by a socket configuration module, a number of CPUs to be utilized during operation of the computing system; determining, by the socket configuration module, performance characteristics associated with each available CPU, the performance characteristics associated with each available CPU including information describing computing devices such as memory devices, input/output (‘I/O) devices, and other downstream devices that are coupled to one or more of the available CPUs; and selecting, by the socket configuration module in dependence upon the performance characteristics associated with each available CPU and a predetermined performance policy, a target CPU to utilize as a boot CPU.

Abstract: Optimizing computer hardware usage in a computing system that includes a plurality of populated central processing unit (‘CPU’) sockets, including: determining, by a socket configuration module, a number of CPUs to be utilized during operation of the computing system; determining, by the socket configuration module, error characteristics associated with each available CPU, wherein the error characteristics associated with each available CPU include error information for computing devices that are coupled to one or more of the available CPUs; and selecting, by the socket configuration module in dependence upon the error characteristics associated with each available CPU and a predetermined error tolerance policy, a target CPU to utilize as a boot CPU.

Abstract: A method includes performing operations on a compute node including a plurality of processors each having a local PCI processing element and a local processor interconnect, wherein the local processor interconnect of each processor is connected to the local processor interconnect of at least one other processor. The method further includes identifying a PCI device that is directly attached to the local PCI processing element of a first one of the processors and positioned in an upstream airflow direction from the first processor. The operating system monitors the PCI device and, in response to determining that the PCI device is performing a power-intensive operation, directs operations away from the first processor to a second one of the processors, wherein the local processor interconnect of the second processor is directly connected to the processor interconnect of the first processor.

Abstract: A hardware system comprises a digital signal generator, which generates a digital electrical signal that describes a first physical state of a first device; an analog electrical signal generator, which generates an analog electrical signal that describes a second physical state of the first device; a hybrid digital state signal generator, which generates a hybrid digital state signal that comprises the analog electrical signal overlaid onto the initial digital electric signal; and a hybrid signal transmitter, which transmits the hybrid digital state signal from the first device to a second device, wherein the second device comprises a hybrid signal receiver/decoder that extracts the analog electrical signal from the hybrid digital state signal.