Abstract: Systems and methods for determining an operational condition of a capacitor package are disclosed. According to an aspect, a system may include a capacitor package including a dielectric material operatively connected between a first terminal and a second terminal. The system may include a Zener diode being operatively connected with its cathode at a third terminal and its anode at the second terminal. The system may also include a test pin being conductively connected to the third terminal. The system may also include a testing module configured to receive an electrical output from the test pin. The testing module may also be configured to determine an operational condition of the capacitor package based on the electrical output. The testing module may further be configured to present the operational condition of the capacitor package.

Abstract: Chip select (‘CS’) multiplication in an SPI system that includes an SPI master, a CS multiplier, a plurality of SPI slaves, and a fall time detection circuit, where the SPI master is coupled to the CS multiplier and the fall time detection circuit by a CS signal line, the CS multiplier includes a plurality of CS outputs with each CS output coupled to an SPI slave, and CS multiplication includes: receiving, from the SPI master, the CS signal on the CS signal line; detecting fall time of the CS signal; and, if the fall time of the CS signal is less than a predefined threshold, configuring, by the fall-time detection circuit, the CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output.

Abstract: According to one exemplary embodiment, a method for load optimization using cable-associated voltage drop is provided. The method may include receiving a plurality of tasks for processing by a plurality of electronic devices. The method may also include determining a power loss value for one or more power cables powering each of the plurality of electronic devices. The method may further include assigning the plurality of tasks to one or more of the plurality of electronic devices based on the power loss value for the one or more power cables powering each of the plurality of electronic devices.

Abstract: Controlling a plurality of serial peripheral interface (‘SPI’) peripherals using a single chip select in a computing system, the computing system including an SPI master, a first SPI peripheral, and a second SPI peripheral, wherein the first SPI peripheral is operatively coupled to the second SPI peripheral, including: receiving, by the first SPI peripheral, a signal from the SPI master; determining, by the first SPI peripheral, whether the first SPI peripheral is a primary SPI peripheral or a backup SPI peripheral; responsive to determining that the first SPI peripheral is the backup SPI peripheral, transmitting, by the first SPI peripheral to the second SPI peripheral, the signal; and responsive to determining that the first SPI peripheral is the primary SPI peripheral: servicing, by the first SPI peripheral, an instruction contained in the signal; and transmitting, by the first SPI peripheral to the second SPI peripheral, a response signal.

Abstract: A method includes regulating voltage to a memory system responsive to a voltage signal received at a voltage feedback line, wherein the memory system includes a plurality of voltage sense line pairs in different locations within the memory system. The method further includes identifying a location of each of a plurality of installed memory modules present in the memory system. Still further, the method includes identifying a voltage sense line pair that provides a shortest aggregate distance to each of the installed memory modules, and then regulating voltage to the memory system responsive to the identified voltage sense line pair.

Abstract: A computer program product includes a computer readable storage medium embodying program instructions executable by a processor to perform a method. The method includes sequentially passing a voltage signal from each voltage sense line pair to a voltage feedback line of a voltage regulator. The voltage regulator controls voltage to the memory system responsive to the voltage signal received at the voltage feedback line, wherein the memory system includes a plurality of voltage sense line pairs in different locations. For each voltage sense line pair, the method identifies a memory margin based on memory operation while regulating voltage responsive to the voltage signal from the voltage sense line pair. The voltage sense line pair that provides the greatest memory margin is identified, and the voltage regulator is made to control voltage to the memory system responsive to the identified voltage sense line pair.

Abstract: Embodiments of the invention provide a method, system and computer program product for dynamically locating a device within a data center. A method for dynamically locating a device within a data center includes wirelessly receiving in a fixed device amongst a multiplicity of devices in a data center, a request from a mobile device to locate a target device amongst the devices. The method also includes broadcasting a request to the multiplicity of devices to establish respective wireless identifiers based upon a proximity of each of the multiplicity of the devices to the target device relative to adjacent ones of the devices. The method yet further includes establishing a wireless identifier for the fixed device based upon a wireless identifier of an adjacent one of the devices. Finally, the method includes returning to the mobile device by the fixed device the established wireless identifier for the fixed device.

Abstract: Systems and methods for allocating memory usage based on voltage regulator efficiency are disclosed. According to an aspect, a method may include receiving a first efficiency value of a first voltage regulator associated with a first memory device among multiple memory devices. The method may also include receiving a second efficiency value of a second voltage regulator associated with a second memory device of the memory devices. The method may also include receiving a request to write data to one of the first memory devices and the second memory device. The method may also include determining whether to write the data to the first memory device or the second memory device based on the first and second efficiency values. Further, the method may include writing the data to the first memory device or the second memory device based on the determination.

Abstract: The present disclosure provides signaling control among multiple communication interfaces of an electronic device based on signal priority. According to an aspect, an electronic device includes multiple communication interfaces. The electronic device also includes a communication controller configured to determine priority of signals to be communicated on different communication interfaces among the plurality of communication interfaces. Further, the communication controller is configured to determine an order of communication of the signals among the different communication interfaces based on the priority of the signals to be communicated. The communication controller is also configured to control communication of the signals among the different communication interfaces based on the determined order of communication.

Abstract: An electronic system comprises: a pin sensor; and an integrated management module, wherein the integrated management module: identifies a location of a damaged connector between a semiconductor chip and a hardware socket, wherein the location of the damaged connector is described by one or more readings from the pin sensor, and wherein the damaged connector prevents a particular signal from being supplied to the semiconductor chip via the hardware socket; identifies the particular signal as an input for a particular semiconductor function; determines whether the semiconductor chip provides the particular semiconductor function; and adjusts a use of the semiconductor chip based on whether or not the semiconductor chip uses the particular signal to provide the particular semiconductor function.

Abstract: A system, method, and/or computer program product comprises an input/output (I/O) bus and an intelligent current bank that couples a voltage source to the I/O bus. The intelligent current bank includes an ammeter that measures a real-time flow of current to the I/O bus. In response to the current to the I/O bus exceeding a predetermined level, an intelligent Pulse-Width Modulator (iPWM) within the intelligent current bank selectively decreases current to one or more electronic devices on the I/O bus by shortening a duty cycle of voltage being received by the iPWM from the voltage source.

Abstract: A method includes regulating voltage to a memory system responsive to a voltage signal received at a voltage feedback line, wherein the memory system includes a plurality of voltage sense line pairs in different locations within the memory system. The method further includes sequentially passing a voltage signal from each of the voltage sense line pairs to the voltage feedback line, and, for each voltage sense line pair, calculating a memory margin of the memory system based on memory operation while regulating voltage to the memory system responsive to the voltage signal from the voltage sense line pair. Still further, the method includes identifying the voltage sense line pair that provides the greatest memory margin, and then regulating voltage to the memory system responsive to the identified voltage sense line pair.

Abstract: A computer program product includes a computer readable storage medium embodying program instructions executable by a processor to perform a method. The method includes sequentially passing a voltage signal from each voltage sense line pair to a voltage feedback line of a voltage regulator. The voltage regulator controls voltage to the memory system responsive to the voltage signal received at the voltage feedback line, wherein the memory system includes a plurality of voltage sense line pairs in different locations. For each voltage sense line pair, the method identifies a memory margin based on memory operation while regulating voltage responsive to the voltage signal from the voltage sense line pair. The voltage sense line pair that provides the greatest memory margin is identified, and the voltage regulator is made to control voltage to the memory system responsive to the identified voltage sense line pair.

Abstract: Controlling power consumption of a voltage regulator in a computer system that includes computer memory and the voltage regulator is configured to provide regulated source voltage to the computer memory includes: receiving, by a voltage regulator controller, memory margin statistics of the computer memory, the memory margin statistics including data describing operational tolerance of the computer memory to source voltage signal variations; and adjusting, by the voltage regulator controller, one or more operating characteristics of the voltage regulator in dependence upon the memory margin statistics.

Abstract: Methods and systems for fan speed control based on memory margin are disclosed. According to an aspect, a method includes determining an operating margin of a memory interface. The method also includes determining whether the operating margin of the memory interface meets a predetermined condition. Further, the method includes controlling a speed of a computing system cooling fan based on the operating margin in response to determining the operating margin meets the predetermined condition.

Abstract: A message is simultaneously broadcast to multiple systems on a 1-wire bus. A first addressed communication session is established between a microprocessor and a first 1-wire I/O expander via a 1-wire bus, where the first 1-wire I/O expander is electrically coupled to a first system. The first 1-wire I/O expander is placed into “fast access mode”, and then removed from the 1-wire bus by opening a switch to the 1-wire bus. A second addressed communication session is established between the microprocessor and a second 1-wire I/O expander before the switch recloses, where the second 1-wire I/O expander is electrically coupled to a second system. The second 1-wire I/O expander is then placed into “fast access mode”. In response to the timer expiring and the switch reclosing, an unaddressed message is broadcast from the microprocessor to the first and second systems via the first and second 1-wire I/O expanders.

Abstract: A system, method, and/or computer program product comprises an input/output (I/O) bus and an intelligent current bank that couples a voltage source to the I/O bus. The intelligent current bank includes an ammeter that measures a real-time flow of current to the I/O bus. In response to the current to the I/O bus exceeding a predetermined level, an intelligent Pulse-Width Modulator (iPWM) within the intelligent current bank selectively decreases current to one or more electronic devices on the I/O bus by shortening a duty cycle of voltage being received by the iPWM from the voltage source.

Abstract: Systems and methods for allocating memory usage based on voltage regulator efficiency are disclosed. According to an aspect, a method may include receiving a first efficiency value of a first voltage regulator associated with a first memory device among multiple memory devices. The method may also include receiving a second efficiency value of a second voltage regulator associated with a second memory device of the memory devices. The method may also include receiving a request to write data to one of the first memory devices and the second memory device. The method may also include determining whether to write the data to the first memory device or the second memory device based on the first and second efficiency values. Further, the method may include writing the data to the first memory device or the second memory device based on the determination.

Abstract: A computer program product includes a computer readable storage medium having program instructions embodied therewith, wherein the program instructions are executable by a processor to cause the processor to perform a method. The method comprises obtaining an activity level for each of a plurality of functions of an integrated circuit, wherein each function has a different physical location on the integrated circuit. The method further includes dynamically adjusting an amount of current supplied to the integrated circuit by each of a plurality of power stages of a DC voltage regulator to meet the current requirements of the plurality of functions and to control power losses between the power stages and the functions, wherein each power stage has a different physical location along a perimeter of the integrated circuit.

Abstract: A method includes obtaining an activity level for each of a plurality of functions of an integrated circuit, wherein each function has a different physical location on the integrated circuit. The method further includes dynamically adjusting an amount of current supplied to the integrated circuit by each of a plurality of power stages of a DC voltage regulator to meet the current requirements of the plurality of functions and to control power losses between the power stages and the functions, wherein each power stage has a different physical location along a perimeter of the integrated circuit.