Abstract: Micro-idle power in a subsystem of a portable computing device may be actively managed based on client voting. Each client vote may include a client activity status indication and a client latency tolerance indication. Votes are aggregated to provide an aggregate client latency tolerance, which may be used to obtain a set of micro-idle time values. Micro-idle timers in the subsystem may be set to associated micro-idle time values. The micro-idle timers determine whether one or more of the micro-idle time values have elapsed. A power management policy associated with each micro-idle time value determined to have elapsed may be applied to a portion of the subsystem.

Abstract: Micro-idle power in a subsystem of a portable computing device may be actively managed based on client voting. Each client vote may include a client activity status indication and a client latency tolerance indication. Votes are aggregated to provide an aggregate client latency tolerance, which may be used to obtain a set of micro-idle time values. Micro-idle timers in the subsystem may be set to associated micro-idle time values. The micro-idle timers determine whether one or more of the micro-idle time values have elapsed. A power management policy associated with each micro-idle time value determined to have elapsed may be applied to a portion of the subsystem.

Abstract: A memory controller is configured to communicate to a DRAM an indication of when a most-recent memory-controller-triggered refresh cycle occurred prior to a transition to a self-refresh mode of operation in which the DRAM self-triggers its refresh cycles.

Abstract: Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received MRW is either ignored or implemented by the first DRAM.

Abstract: Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received. MRW is either ignored or implemented by the first DRAM.

Abstract: Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received MRW is either ignored or implemented by the first DRAM.

Abstract: Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received MRW is either ignored or implemented by the first DRAM.

Abstract: A memory controller is provided to increment a source timestamp count responsive to a clock signal. Further, the memory controller associates the source timestamp count to a respective word for each endpoint in a plurality of endpoints. The memory controller transmits the received clock signal, a respective data word, and an associated source count to each endpoint. Each endpoint increments a destination count responsive to the clock signal. Each endpoint further transmits its respective word to an external memory responsive to the destination count being greater than or equal to the associated source count by a threshold margin.

Abstract: Various embodiments of systems and methods are disclosed for reducing volatile memory standby power in a portable computing device. One such method involves receiving a request for a volatile memory device to enter a standby power mode. One or more compression parameters are determined for compressing content stored in a plurality of banks of the volatile memory device. The stored content is compressed based on the one or more compression parameters to free-up at least one of the plurality of banks. The method disables self-refresh of at least a portion of one or more of the plurality of banks freed-up by the compression during the standby power mode.

Abstract: A memory controller is configured to communicate to a DRAM an indication of when a most-recent memory-controller-triggered refresh cycle occurred prior to a transition to a self-refresh mode of operation in which the DRAM self-triggers its refresh cycles.

Abstract: A memory controller is provided to increment a source timestamp count responsive to a clock signal. Further, the memory controller associates the source timestamp count to a respective word for each endpoint in a plurality of endpoints. The memory controller transmits the received clock signal, a respective data word, and an associated source count to each endpoint. Each endpoint increments a destination count responsive to the clock signal. Each endpoint further transmits its respective word to an external memory responsive to the destination count being greater than or equal to the associated source count by a threshold margin.

Abstract: A method for data synchronization is provided according to certain embodiments. The method comprises receiving data, a data clock signal, and a clean clock signal, sampling the data using the data clock signal, synchronizing the sampled data with the clean clock signal, and outputting the synchronized sampled data. The method also comprises tracking a phase drift between the data clock signal and the clean clock signal, and pulling in the output of the synchronized sampled data by one clock cycle of the clean clock signal if the tracked phase drift reaches a first value in a first direction.

Abstract: Aspects include computing devices, systems, and methods for reorganizing the storage of data in memory to energize less than all of the memory devices of a memory module for read or write transactions. The memory devices may be connected to individual select lines such that a re-order logic may determine the memory devices to energize for a transaction according to a re-ordered memory map. The re-order logic may re-order memory addresses such that memory address provided by a processor for a transaction are converted to the re-ordered memory address according to the re-ordered memory map without the processor having to change its memory address scheme. The re-ordered memory map may provide for reduced energy consumption by the memory devices, or a balance of energy consumption and performance speed for latency tolerant processes.

Abstract: Various embodiments of systems and methods are disclosed for reducing volatile memory standby power in a portable computing device. One such method involves receiving a request for a volatile memory device to enter a standby power mode. One or more compression parameters are determined for compressing content stored in a plurality of banks of the volatile memory device. The stored content is compressed based on the one or more compression parameters to free-up at least one of the plurality of banks. The method disables self-refresh of at least a portion of one or more of the plurality of banks freed-up by the compression during the standby power mode.

Abstract: A method and system for managing safe downtime of shared resources within a portable computing device are described. The method may include determining a tolerance for a downtime period for an unacceptable deadline miss element of the portable computing device. Next, the determined tolerance for the downtime period may be transmitted to quality-of-service (“QoS”) controller. The QoS controller may determine if the tolerance for the downtime period needs to be adjusted. The QoS controller may receive a downtime request from one or more shared resources of the portable computing device. The QoS controller may determine if the downtime request needs to be adjusted. Next, the QoS controller may select a downtime request for execution and then identify which one or more unacceptable deadline miss elements of the portable computing device that are impacted by the selected downtime request.

Abstract: Method and apparatus for signal sampling timing drift compensation are provided. Raw time values or deviations between clock and data are measured and filtered to generate filtered time information, and the filtered time information is compared to an upper bound and a lower bound. If the filtered time information is outside the upper and lower bounds, then an amount of timing compensation for the clock is computed. A signal is sent to reset the clock based on the amount of timing compensation.

Abstract: A method includes detecting, at a controller, a rate-of-change between first data traffic to be sent to a dynamic random access memory (DRAM) at a first time and second data traffic to be sent to the DRAM at a second time. The method also includes adjusting a data rate of the second data traffic in response to a determination that the rate-of-change satisfies a threshold.

Abstract: A method for data synchronization is provided according to certain embodiments. The method comprises receiving data, a data clock signal, and a clean clock signal, sampling the data using the data clock signal, synchronizing the sampled data with the clean clock signal, and outputting the synchronized sampled data. The method also comprises tracking a phase drift between the data clock signal and the clean clock signal, and pulling in the output of the synchronized sampled data by one clock cycle of the clean clock signal if the tracked phase drift reaches a first value in a first direction.

Abstract: In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the clean clock signal, wherein the synchronization circuit is further configured to sample the data using the data clock signal, and to synchronize the sampled data with the clean clock signal.

Abstract: Aspects include computing devices, systems, and methods for reorganizing the storage of data in memory to energize less than all of the memory devices of a memory module for read or write transactions. The memory devices may be connected to individual select lines such that a re-order logic may determine the memory devices to energize for a transaction according to a re-ordered memory map. The re-order logic may re-order memory addresses such that memory address provided by a processor for a transaction are converted to the re-ordered memory address according to the re-ordered memory map without the processor having to change its memory address scheme. The re-ordered memory map may provide for reduced energy consumption by the memory devices, or a balance of energy consumption and performance speed for latency tolerant processes.