Abstract: A system and method are provided for periodically servicing a channel in a timer used for controlling events. The method services a channel in a fixed periodic cycle, and reads a first control word loaded in the channel to determine a timer operation. Then, a first data word in the channel is managed in response to the determined operation. In one aspect, a clock signal is supplied with a fixed period. Then, servicing the channel in a fixed periodic cycle includes: establishing a cycle having a first number of clock signals; and, servicing the channel for a second number of clock signals each cycle. If the timer includes a plurality of channels, then each channel is serially serviced in a single cycle.

Abstract: A method and apparatus for providing bus protocol simulation in a multi-processor data processing system (10). A plurality of edge interface circuits (14,16) are used to interface a first bus (32, 34, 36), which uses a first bus protocol, with a plurality of data processors (50-65), each of which uses a second bus protocol. A memory (90) within each edge interface circuit (14,16) is loaded with a plurality of values. Each of the plurality of values has a control portion and a data portion. The control portion of memory entry "N" is used to initiate the transfer of the data from memory entry "N+1". In an alternate embodiment, multi-processor data processing system (210) includes a plurality of data processors (250-258) and a plurality of edge interface circuits (214-217).

Abstract: A method for complex data movement in a multi-processor data processing system. In one embodiment, the multi-processor data processing system (10) includes an array (12) of data processors (50-65), a plurality of edge interface circuits (14,16), and a bus interface controller (22). In an alternate embodiment, multiprocessor data processing system (210) includes an array (212) of data processors (250-258), a plurality of edge interface circuits (214-217), and a bus interface controller (222). The data processing systems (10,210) are capable of performing complex data movement patterns between the processors (50-65,250-258) and the corresponding edge interface circuits (14, 16, 214-217), such as a transpose pattern, a ping-pong pattern, and a checkerboard pattern.

Abstract: A multi-processor data processing system (10) includes an array (12) of one or more data processors (50-65). Data processing system (10) has edge interface circuits (14,16) for transferring control and data to and from the array (12). A data bus (32), an address bus (34), and a control bus (36) each transfers information to and from the array (12), the edge interfaces (14,16), and a bus interface controller (22). In an alternate embodiment, multi-processor data processing system (210) includes an array (212) of one or more data processors (250-258). Data processing system (210) has edge interfaces (214-217) for transferring control and data to and from the array (212). A data bus (232), an address bus (234), and a control bus (236) each transfers information to and from the array (212), the edge interfaces (214-217), and a bus interface controller (222).

Abstract: A mode selection circuit is disclosed which is suitable for configuring a data processor at the time at which the data processor is initialized with a reset signal. Mode selection latches are coupled to terminals normally used as an input/output port for the data processor and the latches are clocked with a signal generated by a level detector circuit which senses the reset signal. The mode selection latches are programmed by applying appropriate logic levels to the terminals of the input/output port at the time at which the data processor is being reset. The circuitry is adapted for allowing the connection of a diode from a terminal of the input/output port to the reset terminal of the data processor in order to program a low logic level into the corresponding mode detection latch.

Abstract: A microprocessor on a monolithic integrated circuit is provided having a single clock input pin for receiving a clock input signal. The clock input signal is used to gate address data onto the address bus and to enable a data input dynamic latch. In addition the input clock signal is used to generate two complementary non-overlapping clock signals used for synchronizing purposes within the microprocessor.

Abstract: A digital data processor on a single monolithic integrated circuit chip is provided which uses one less pin. The elimination of the pin is accomplished by using, internally to the processor, a valid memory address signal to gate information from the address but to an address output line. Whenever an address is not present on the address bus all logic "1's" are generated on the address output bus.

Abstract: A microprocessor interconnected to a RAM on the same integrated circuit chip. Interconnect circuitry connects the RAM to the microprocessor data bus to allow RAM data to be transferred to an instruction register of the microprocessor which permits the RAM to contain instructions and operation codes. A sense amplifier is used to provide an output from the RAM. At least one buffer is coupled to the output of the sense amplifier. A bilateral switch is coupled to the at least one buffer and controllably switches the output of the at least one buffer to the microprocessor internal data bus and to an external data bus.

Abstract: A microprocessor comprises an internal address bus having a first portion (2,4) having a plurality of conductors carrying the low order address byte and a second portion (10) having a plurality of conductors for carrying the high order address byte. The microprocessor further comprises a plurality of registers, including an incrementor (12,13), a program counter (14,15), a temporary register (16,17), a stack pointer (18,19), an index register (20,21), and an accumulator (22,24), each comprising a pair of 8-bit registers for temporarily storing information. An arithmetic logic unit (28) performs computational operations on digital information within the microprocessor. The microprocessor includes a pair of internal data buses (6,8) each having a plurality of conductors for conducting digital information within the microprocessor. Means are provided for coupling selected ones of the registers, or the high or low order portions thereof, to the first and second data buses.

Abstract: A digital system including a plurality of metal-oxide-semiconductor (MOS) chip random access memories (RAM), read only memories (ROM) and peripheral interface adaptors coupled to a common bidirectional data bus which is coupled to and controlled by a microprocessor unit (MPU). Each peripheral interface adaptor includes a control register loadable under program control. The contents of the control register control selection of several registers within the interface adaptor. The control register also controls other functions of the peripheral interface adaptor, including determining direction of data movement at the peripheral buffers of the interface adaptor. The contents of the control register of each interface adaptor are monitorable by the microprocessor unit.

Abstract: A peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA.The peripheral interface adaptor includes a plurality of system data bus buffer circuits coupled to a system data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral data bus. The direction of data flow in the peripheral data bus is controlled by a data direction register. Data from the system data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to the control register, a data direction register and a data register. Data from the peripheral data bus, the data direction register and the control register are transferred via an output bus to the system data bus buffers.

Abstract: A circuit and a method for adding an 8-bit operand to a 16-bit operand are disclosed such that the number of machine cycles required by a data processor to perform such an addition is reduced. The 8-bit operand and the least significant byte of the 16-bit operand are added together within an 8-bit adder circuit to generate the least significant byte of the result. Simultaneously, the most significant byte of the 16-bit operand is stored in a temporary register and is also input to an increment/decrement network. The adder circuit, after a given delay time, generates a carry signal depending on whether a carry-out was produced by the addition. The carry signal and the sign bit of the 8-bit operand control the mode of operation of the increment/decrement network and determine whether the increment/decrement network or the temporary register will be selected to provide the most significant byte of the result.

Abstract: The peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA.A peripheral interface adaptor includes a plurality of data bus buffer circuits coupled to a bidirectional data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral system data bus. A direction of data flow at the peripheral interface data bus is controlled by a data direction register. Data from the data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to the control register, a data direction register and a data register. Data from the peripheral data bus, the data direction register, and the control register are transferred via the output bus to the data bus buffers.

Abstract: An N-channel field effect transistor microprocessor includes an arithmetic logic unit, a plurality of working registers and address generating circuitry coupled to an internal bus. Control circuitry is coupled to the arithmetic logic unit, the working registers, and the address generating circuitry for producing control signals for controlling operation of the arithmetic logic unit, the working registers, and the address generating circuitry. The microprocessor requires only a single external power supply, and includes means connected to the external power supply for providing electrical energy to the working registers, the arithmetic logic unit, the control circuitry, and the address generating circuitry in order to effect operation thereof.

Abstract: A digital system includes a microprocessor coupled to a data bus and an address bus. A memory for storing data and instructions is connected to the data bus and the address bus. A peripheral device is connected to an interface adaptor. The interface adaptor is connected to the data bus and the address bus, and performs the function of interfacing between the digital system and a peripheral device, such as a printer or a display device. The microprocessor includes logic circuitry for generating a Valid Memory Address (VMA) output. The VMA output is used to generate an enable signal applied to the memory and the adaptor to enable the memory and the adaptor to be accessed by the microprocessor when the binary address on the address bus is valid and to prevent the memory and the adaptor from being accessed by the microprocessor when the binary address on the address bus is not valid with respect to the microprocessor.

Abstract: A microprocessor system includes a microprocessor, a memory, and an interface adaptor all coupled to a data bus. The interface adaptor is coupled between the data bus and a peripheral device, such as a teleprinter. A first interrupt conductor is connected to the peripheral device and to interrupt logic circuitry in the interface adaptor. A second interrupt conductor is connected to the microprocessor and the interrupt logic circuitry. The interrupt logic circuitry is also coupled to and interrogatable by the microprocessor via the data bus. The interrupt logic circuitry stores interrupt contrl information from the data bus, and generates a second interrupt signal on the second interrupt conductor in response to the stored interrupt control information and an interrupt signal generated on the first interrupt conductor by the peripheral device.

Abstract: A peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA.A peripheral interface adaptor includes a plurality of data bus buffer circuits coupled to a bidirectional data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral data bus. A direction of data flow at the peripheral interface data bus is controlled by a data direction register. Data from the data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to the control register, the data direction register and a data register. Data from the peripheral data bus the data direction register and the control register are transferred via the output bus to the data bus buffers.

Abstract: A digital system comprises a plurality of metal-oxide-semiconductors (MOS) chip random access memory (RAM) and read only memory (ROM) and peripheral interface adaptor circuits used as part of the computer coupled to a common bidirectional data bus which is coupled to and controlled by a microprocessor unit (MPU) chip. In the digital system, data transfers on the common bidirectional data bus are accomplished without the use of a memory synchronization signal so that a special signal conductor indicating when the memory is ready to transfer data is not required. This is accomplished by logic circuitry which expands a clock signal pulse which is applied to the microprocessor chip whenever a memory location is addressed which has a longer access time than is consistent with the width of the pulse ordinarily applied to the microprocessor to effect its operation.

Abstract: A microprocessor includes a data bus and an address bus. The address bus has first and second sections coupled together in series by bus switch circuitry. The microprocessor also includes control circuitry for controlling various data transfers in the microprocessor. The bus switch circuitry includes a plurality of MOSFETs each having their gate electrodes coupled to the control circuitry and having their sources and drains coupled to corresponding bus conductors of the first and second sections of the address bus. A program counter, incrementer and other working registers are coupled between the address bus first section and the data bus. An accumulator register and an arithmetic logic unit are coupled between the second section of address bus and the data bus. An index register for storing information to be utilized in an indexed addressing mode of operation is coupled to both the first and second sections of the address bus and to the data bus.

Abstract: Interrupt circuitry is provided for an MOS integrated circuit microprocessor chip. An input of the microprocessor chip is adapted to having an external interrupt signal applied thereto for interrupting the operation of the microprocessor chip within a digital data processing system. The input is coupled to circuitry which inhibits loading of the next instruction to be executed in response to an interrupt request signal applied to the interrupt request input, and also forces a code into the instruction register in response to the interrupt request signal. The code is substantially similar to the code for a software wait instruction or a software interrupt instruction. Therefore, much of the same circuitry within the microprocessor can be used for executing an interrupt operation, a software wait instruction, or a software interrupt instruction.