Abstract: A method of generating addresses in a microprocessor includes steps of storing first informationrepresentative of a first address in a first register, such as a program counter register. The first information is transmitted to a first address bus in order to effect addressing the contents of a first location represented by the first address. The first information is also transmitted via the address bus to an incrementor-decrementor circuit. The first information is incremented to produce second information representative of the address of the next instruction during the addressing of the first location. The second information is then transmitted to the first register.

Abstract: A processor including a first bus, a second bus, and a control circuit for producing control signals includes a counter having a plurality of inputs and outputs responsive to the control circuit and coupled between the first and second buses for incrementing digital information present at the inputs of the counter. The processor includes a first coupling circuit responsive to the control circuit for coupling the counter inputs to the first bus to effect transferring digital information from the first bus to the counter inputs. A second coupling circuit couples the counter inputs to the second bus to transfer digital information from the second bus to the counter inputs in response to the control circuit. A third coupling circuit couples the counter outputs to the second bus to transfer digital information from the counter output to the second bus.

Abstract: An interface adaptor suitable for use in a microprocessor system includes an input register coupled to a bidirectional data bus of the microprocessor system. The interface adaptor includes a plurality of registers, including a control register and a data register, coupled to the input register by means of an internal input bus. Each of the plurality of registers includes flip-flops which are coupled as slave flip-flops to corresponding flip-flops of the input register. The corresponding flip-flops of the input register function as master flip-flops. The interface adaptor also includes register selection logic circuitry for selecting one of the plurality of registers by electrically coupling its slave flip-flop to the corresponding master flip-flops of the input register.

Abstract: A microprocessor includes a data bus and an address bus. The address bus has first and second sections coupled together in series by bus switch circuitry. The microprocessor also includes control circuitry for controlling various data transfers in the microprocessor. The bus switch circuitry includes a plurality of MOSFETs each having their gate electrodes coupled to the control circuitry and having their sources and drains coupled to corresponding bus conductors of the first and second sections of the address bus. A program counter, incrementer and other working registers are coupled between the address bus first section and the data bus. An accumulator register and an arithmetic logic unit are coupled between the second section of address bus and the data bus.

Abstract: Interrupt circuitry is provided for an MOS integrated circuit microprocessor chip. An input of the microprocessor chip is adapted to having an external interrupt signal applied thereto for interrupting the operation of the microprocessor chip within a digital data processing system. This first input is connected to circuitry which is enabled by a signal from a bit of a condition code register on the microprocessor chip which bit, is set, acts to mask or disenable the interrupt signal, so that the instruction execution operation of the microprocessor chip is not interrupted. A second input of a microprocessor chip is adapted to having a second interrupt signal applied thereto. The second input is connected to other input circuitry which is not enabled by the mask bit of a condition code register. Therefore, the second input acts as a non-maskable interrupt input.

Abstract: A digital system comprises a plurality of metal-oxide-semiconductors (MOS) chip random access memory (RAM) and read only memory (ROM) and peripheral interface adaptor circuits used as part of the computer coupled to a common bidirectional data bus which is coupled to and controlled by a microprocessor unit (MPU) chip. The digital system uses a multi-level interrupt circuit arrangement including a masked interrupt request input responsive to a multi-plexed interrupt request from peripheral circuits of the system and a non-masked interrupt request input which activates circuitry internal to the microprocessor chip for bypassing program control in initiating an interrupt sequence.

Abstract: A program register is coupled between a data bus N bits wide and an address bus N bits wide for storing the address of the current byte of a multi-byte instruction currently being executed. A counter is also coupled between the address bus and the data bus and is additionally coupled to a program register to allow loading of the counter contents into the program register independently of the status of the address bus. An auxiliary register is also coupled between the address bus and the data bus. The counter is updated every machine cycle during execution of the instruction, except for certain instructions during which the counter is inhibited to allow it to function as an auxiliary register, thereby storing the address of the next instruction. For certain instructions, the address bus is utilized for data transfers to or from the auxiliary register simultaneously with loading of the program register from the counter, depending on the type of instruction being executed.

Abstract: Interrupt circuitry is provided for an MOS integrated circuit microprocessor chip. An input of the microprocessor chip is adapted to having an external interrupt signal applied thereto for interrupting the operation of the microprocessor chip within a digital data processing system. This first input is connected to circuitry which is enabled by a signal from a bit of a condition code register on the microprocessor chip which bit, is set, acts to mask or disenable the interrupt signal, so that the instruction execution operation of the microprocessor chip is not interrupted. A second input of a microprocessor chip is adapted to having a second interrupt signal applied thereto. The second input is connected to other input circuitry which is not enabled by the mask bit of a condition code register. Therefore, the second input acts as a non-maskable interrupt input.

Abstract: A peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA. The peripheral interface adaptor includes a plurality of data bus buffer circuits coupled to a bidirectional system data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral data bus. A direction of data flow at the peripheral interface data bus is controlled by a data direction register. Data from the data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to a control register, the data direction register and a data register. Data from the peripheral data bus, the data direction register, and the control register are transferred via the output bus to the data bus buffers.

Abstract: A digital filter comprising an up-down counter conditioned by a signal indicative of whether an input periodic oscillation signal is of a frequency representing a binary 1 or a binary 0, to count in one direction to a threshold count for an input 1, and to count in the other direction to a threshold count for an input 0 is disclosed. Additional, a crystal controlled oscillator provides the pulses by which the up-down counter counts in a direction determined by the conditioning signal. The conditioning signal is provided by a storage flip-flop which is conditioned by an indicia signal flip-flop from the demodulation receiver.