Abstract: A computer implemented method, data processing system, and processor are provided for tracing thermal data via performance monitoring. A performance monitor is set into a tracing mode. Temperatures are sensed by a digital thermal sensor over a time period. The sensed temperatures are stored in a data structure and a trace of the sensed temperatures is graphically displayed.

Abstract: A method for providing an alternate keypad arrangement in a virtual keypad is presented. In the alternate keypad arrangement, the virtual keys are laid out in a non-sequential arrangement. In one embodiment, the labels displayed on the virtual keys appear sequential, however the values registered when the user presses the virtual key does not match the label and, hence, the values are laid out in a non-sequential manner. Using alternate keypad arrangements arranged in patterns enables the user to use a common pattern, or patterns easily remembered by the user, for a wide variety of authentication data used to access a wide variety of systems. Rather than remembering the specific PIN codes and passwords, the user simply remembers a pattern and selects virtual keys that match the pattern.

Abstract: A computer implemented method, data processing system, and processor are provided for thermal interrupt generation. An interrupt temperature is set to a first temperature and an interrupt direction is to a greater than or equal to determination. A determination is made as to whether a sensed temperature from a digital thermal sensor meets or exceeds the interrupt temperature in response to the interrupt direction. A first interrupt is generated in response to the sensed temperature meeting or exceeding the interrupt temperature.

Abstract: A computer implemented method is provided for tracing thermal data via performance monitoring. A performance monitor is set into a tracing mode. Temperatures are sensed by a digital thermal sensor over a time period. The sensed temperatures are stored in a data structure and a trace of the sensed temperatures is graphically displayed as the sensed temperatures are being stored.

Abstract: A computer implemented method, data processing system, and processor are provided for managing a thermal management system. A determination is made as to whether a plurality of digital thermal sensors is faulty or functional. A power savings mode of at least one unit within the integrated circuit associated with the functional digital thermal sensor is monitored in response to at least one of the plurality of digital thermal sensors being functional. A functional digital thermal sensor is disabled in response to the at least one unit being in a power savings mode.

Abstract: A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.

Abstract: A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.

Abstract: A computer implemented method, data processing system, and processor are provided for logging a maximal temperature in an integrated circuit. A digital thermal sensor senses a temperature in the integrated circuit. The sensed temperature of the digital thermal sensor is read and a determination is made as to whether the sensed temperature is higher than a current maximal temperature. The sensed temperature is logged in response to the sensed temperature being higher than the current maximal temperature. The sensed temperature becomes a new maximal temperature for the integrated circuit.

Abstract: A computer implemented method, data processing system, and processor are provided for logging a maximal temperature in an integrated circuit. A digital thermal sensor senses a temperature in the integrated circuit. The sensed temperature of the digital thermal sensor is read and a determination is made as to whether the sensed temperature is higher than a current maximal temperature. The sensed temperature is logged in response to the sensed temperature being higher than the current maximal temperature. The sensed temperature becomes a new maximal temperature for the integrated circuit.

Abstract: A system and method for providing an alternate keypad arrangement in a virtual keypad is presented. In the alternate keypad arrangement, the virtual keys are laid out in a non-sequential arrangement. In one embodiment, the labels displayed on the virtual keys appear sequential, however the values registered when the user presses the virtual key does not match the label and, hence, the values are laid out in a non-sequential manner. Using alternate keypad arrangements arranged in patterns enables the user to use a common pattern, or patterns easily remembered by the user, for a wide variety of authentication data used to access a wide variety of systems. Rather than remembering the specific PIN codes and passwords, the user simply remembers a pattern and selects virtual keys that match the pattern.

Abstract: The present invention provides for a circuit for transitioning clocking speeds. A counter is coupled to the clocking means. A comparator is coupled to an output of the counter. A first divider is coupled to the output of the counter. A processor means is coupled to the output of the first divider, thereby lessening current surges.

Abstract: A component of a microprocessor-based data processing system, which includes features for regulating power consumption in snoopable components and has gating off memory coherency properties, is determined to be in a relatively inactive state and is transitioned to a non-snoopable low power mode. Then, when a snoop request occurs, a retry protocol is sent in response to the snoop request. In conjunction with the retry protocol, a signal is sent to bring the component into snoopable mode. When the retry snoop is requested, the component is in full power mode and can properly respond to the snoop request. After the snoop request has been satisfied, the component again enters into a low power mode.

Abstract: A computer implemented method, data processing system, and processor are provided for logging a maximal temperature in an integrated circuit. A digital thermal sensor senses a temperature in the integrated circuit. The sensed temperature of the digital thermal sensor is read and a determination is made as to whether the sensed temperature is higher than a current maximal temperature. The sensed temperature is logged in response to the sensed temperature being higher than the current maximal temperature. The sensed temperature becomes a new maximal temperature for the integrated circuit.

Abstract: A component of a microprocessor-based data processing system, which includes features for regulating power consumption in snoopable components and has gating off memory coherency properties, is determined to be in a relatively inactive state and is transitioned to a non-snoopable low power mode. Then, when a snoop request occurs, a retry protocol is sent in response to the snoop request. In conjunction with the retry protocol, a signal is sent to bring the component into snoopable mode. When the retry snoop is requested, the component is in full power mode and can properly respond to the snoop request. After the snoop request has been satisfied, the component again enters into a low power mode. Therefore, the component is able to enter into a low power mode in between snoops.

Abstract: The present invention provides for a circuit for transitioning clocking speeds. A counter is coupled to the clocking means. A comparator is coupled to an output of the counter. A first divider is coupled to the output of the counter. A processor means is coupled to the output of the first divider, thereby lessening current surges.

Abstract: A system and method for advanced logic built-in self test with selection of scan channels is present. An LBIST controller loads scan patterns into a device's scan channels through sequential or interleaved loading techniques in order to minimize instantaneous power requirements. During interleave loading, the LBIST controller loads a scan bit into a first scan chain, then into a second scan chain, etc. until one bit is loaded into each scan chain. The LBIST controller then returns to load another scan bit into the first scan channel, then the second scan channel, etc. During sequential loading, the LBIST controller loads an entire scan pattern into a first scan chain (one bit per clock cycle). Once the first scan pattern is loaded, the LBIST controller proceeds to load subsequent scan patterns into corresponding scan chains on a one bit per scan channel per clock cycle basis.

Abstract: An apparatus, a method, and a computer program are provided for the generation of constant incremental increases while changing core clock frequencies. In computer systems, oftentimes frequency changes are useful. Maintaining the clocking ability of the computer system, though, can be a difficult task. To maintain the time keeping ability, time base logic is utilized with the free-running clock, which can be frequency limited. However, a plurality of communication channels in conjunction with an adder system is employed to effectively adjust for an ever increasing frequency to allow for a effective timekeeping regardless of the core frequency.

Abstract: The present invention provides for controlling the power consumption of an element. A first power control command is issued by software for the element. It is determined if the power control command corresponds to an allowable power control state for that element as defined by the hardware. If the power control command is not an allowable power control state for that element, the hardware sets the power control at a higher level than the power control state issued by the software. The software is real time software, and the software also sets minimally acceptable activity control states. A hierarchy of power consumption is defined for different elements of a chip by software, which provides the minimum level of power consumption by any element or sub-element on a chip.

Abstract: An apparatus, a method, and a computer program are provided to disable clock distribution. In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Disabling the clock distribution system, however, has been difficult because of the usual requirement for a separate clock for control logic. Therefore, combinational logic can be employed to disrupt the clock distribution and allow a processor to be awakened without a need for a separate clock.

Abstract: A method, computer program product, and apparatus for obtaining a digital temperature reading from within an integrated circuit. In a preferred embodiment, a temperature-stable constant current source is applied to a tapped series of resistors to obtain a set of stable reference voltages. These reference voltages are fed into an analog multiplexer, which selects a single reference voltage to output to a comparator. A PTAT (proportional to absolute temperature) voltage signal is also applied to the comparator, so that the output of the comparator indicates a comparison between the selected reference voltage and the PTAT signal. A digital temperature reading is obtained by using finite-state control to apply test values to the multiplexer in order to search for a value corresponding to a reference voltage that is closest to the value of the PTAT signal. The value that is found is a digital representation of the temperature.