Abstract: To facilitate an efficient processing of contended cache lines, a cache controller that is associated with a requestor receives a fetch request for data from the requestor. The fetch request is associated with a cache scope designation. If the data is in a high-level cache (e.g., L1 cache) associated with the requestor, the cache controller returns the requested data to the requestor. If the data is not in the high-level cache or if the data is not within the cache pool identified by the cache scope of search designation, and/or if obtaining the data is contentious, the controller returns a cache miss, undeliverable data, and request done instruction to the requestor. Such scheme allows or permits address contention events when the requestor deems such events are necessary and/or when important. As such, address contention events, performance, latencies, increased executions times, inefficient use of resources, may be diminished.

Abstract: To facilitate an efficient processing of contended cache lines, a cache controller that is associated with a requestor receives a fetch request for data from the requestor. The fetch request is associated with a cache scope designation. If the data is in a high-level cache (e.g., L1 cache) associated with the requestor, the cache controller returns the requested data to the requestor. If the data is not in the high-level cache or if the data is not within the cache pool identified by the cache scope of search designation, and/or if obtaining the data is contentious, the controller returns a cache miss, undeliverable data, and request done instruction to the requestor. Such scheme allows or permits address contention events when the requestor deems such events are necessary and/or when important. As such, address contention events, performance, latencies, increased executions times, inefficient use of resources, may be diminished.

Abstract: The present disclosure relates to a method for a computer system comprising a plurality of processor cores including a first processor core and a second processor core, wherein a data item is exclusively assigned to the first processor core, of the plurality of processor cores, for executing an atomic primitive by the first processor core. The method includes receiving by the first processor core, from the second processor core, a request for accessing the data item, and in response to determining by the first processor core that the executing of the atomic primitive is not completed by the first processor core, returning a rejection message to the second processor core.

Abstract: Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data.

Abstract: The present disclosure relates to a method for a computer system comprising a plurality of processor cores, including a first processor core and a second processor core, wherein a cached data item is assigned to a first processor core, of the plurality of processor cores, for exclusively executing an atomic primitive. The method includes receiving, from a second processor core at a cache controller, a request for accessing the data item, and in response to determining that the execution of the atomic primitive is not completed by the first processor core, returning a rejection message to the second processor core.

Abstract: Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data.

Abstract: Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data. In response to the memory address matching a memory address stored in the shared controller, the shared controller acknowledges the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets. In response to release of the data by a second requesting agent, the shared controller transmits the data to the first requesting agent.

Abstract: Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data. In response to the memory address matching a memory address stored in the shared controller, the shared controller acknowledges the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets. In response to release of the data by a second requesting agent, the shared controller transmits the data to the first requesting agent.

Abstract: The present disclosure relates to a method for a computer system comprising a plurality of processor cores, wherein a cached data item is assigned to a first core of the processor cores for exclusively executing an atomic primitive by the first core. The method comprises, while the execution of the atomic primitive is not completed by the first core, receiving from a second core at a cache controller a request for accessing the data item. In response to determining that a second request of the data item is received from a third core, of the plurality of processor cores, before receiving the request of the second core, a rejection message may be returned to the second core.

Abstract: The present disclosure relates to a method for a computer system comprising a plurality of processor cores, including a first processor core and a second processor core, wherein a cached data item is assigned to a first processor core, of the plurality of processor cores, for exclusively executing an atomic primitive. The method includes receiving, from a second processor core at a cache controller, a request for accessing the data item, and in response to determining that the execution of the atomic primitive is not completed by the first processor core, returning a rejection message to the second processor core.

Abstract: The present disclosure relates to a method for a computer system comprising a plurality of processor cores including a first processor core and a second processor core, wherein a data item is exclusively assigned to the first processor core, of the plurality of processor cores, for executing an atomic primitive by the first processor core. The method includes receiving by the first processor core, from the second processor core, a request for accessing the data item, and in response to determining by the first processor core that the executing of the atomic primitive is not completed by the first processor core, returning a rejection message to the second processor core.

Abstract: Methods and apparatuses for performing a quiesce operation in a multithread environment is provided. A processor receives a first thread quiesce request from a first thread executing on the processor. A processor sends a first processor quiesce request to a system controller to initiate a quiesce operation. A processor performs one or more operations of the first thread based, at least in part, on receiving a response from the system controller.

Abstract: In an approach for managing data transfer across a bus shared by processors, a request for a first set of data is received from a first processor. A request for a second set of data is received from a second processor. First portions of the first set of data and the second set of data are written to a buffer. Additional portions of each set of data are written to the buffer as portions are received. It is determined that a portion of the first set of data has a higher priority to the bus than a portion of the second set of data based on a priority scheme, wherein the priority scheme is based on return progress of each respective set of data having at least a portion of data in the buffer. The portion of the first set of data is granted access to the bus.

Abstract: Methods and apparatuses for performing a quiesce operation in a multithread environment is provided. A processor receives a first thread quiesce request from a first thread executing on the processor. A processor sends a first processor quiesce request to a system controller to initiate a quiesce operation. A processor performs one or more operations of the first thread based, at least in part, on receiving a response from the system controller.

Abstract: In an approach for managing data transfer across a bus shared by processors, a request for a first set of data is received from a first processor. A request for a second set of data is received from a second processor. First portions of the first set of data and the second set of data are written to a buffer. Additional portions of each set of data are written to the buffer as portions are received. It is determined that a portion of the first set of data has a higher priority to the bus than a portion of the second set of data based on a priority scheme, wherein the priority scheme is based on return progress of each respective set of data having at least a portion of data in the buffer. The portion of the first set of data is granted access to the bus.

Abstract: Aspects include techniques for implementing a clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry for encoding and correction of a chip. A computer-implemented method may include initializing a scan of the chip including data and a set of check bits protecting the data; applying a global control bit to a latch on the chip; and applying an additional clock to the latch so the check bits are updated using the on-chip circuitry.

Abstract: Aspects include techniques for implementing a clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry for encoding and correction of a chip. A computer-implemented method may include initializing a scan of the chip including data and a set of check bits protecting the data; applying a global control bit to a latch on the chip; and applying an additional clock to the latch so the check bits are updated using the on-chip circuitry.

Abstract: Aspects include techniques for bypassing an encoded latch on a chip during a test-pattern scan and using on-chip circuitry to generate a desired encoded pattern, which is inserted into a scan-bypassed latch, to test the on-chip circuitry for defects. A computer-implemented method may include applying a global control bit to the chip; initializing a scan of the chip while bypassing the encoded latch; and applying an extra scan clock to initiate the encoded latch after completing the scan, wherein the encoded latch is updated with check bits generated by the on-chip circuitry.

Abstract: Aspects include techniques for bypassing an encoded latch on a chip during a test-pattern scan and using on-chip circuitry to generate a desired encoded pattern, which is inserted into a scan-bypassed latch, to test the on-chip circuitry for defects. A computer-implemented method may include applying a global control bit to the chip; initializing a scan of the chip while bypassing the encoded latch; and applying an extra scan clock to initiate the encoded latch after completing the scan, wherein the encoded latch is updated with check bits generated by the on-chip circuitry.

Abstract: In an approach for managing data transfer across a bus shared by processors, a request for a first set of data is received from a first processor. A request for a second set of data is received from a second processor. First portions of the first set of data and the second set of data are written to a buffer. Additional portions of each set of data are written to the buffer as portions are received. It is determined that a portion of the first set of data has a higher priority to the bus than a portion of the second set of data based on a priority scheme, wherein the priority scheme is based on return progress of each respective set of data having at least a portion of data in the buffer. The portion of the first set of data is granted access to the bus.