Abstract: A memory system is provided. The memory system includes a memory element that is configured to selectively output data stored to and data fetched from the memory element. An error checking station is configured to receive the data stored to and the data fetched from the memory element. The error checking station is further configured to perform error checking on the data.

Abstract: A mechanism for dynamically altering a request received at a hardware component is provided. The request is received at the hardware component, and the request includes a mode option. It is determined whether an action of the request requires an unavailable resource and it is determined whether the mode option is for the action requiring the unavailable resource. In response to the mode option being for the action requiring the unavailable resource, the action is automatically removed from the request. The request is passed for pipeline arbitration without the action requiring the unavailable resource.

Abstract: Dynamic allocation of cache buffer slots includes receiving a request to perform an operation that requires a storage buffer slot, the storage buffer slot residing in a level of storage. The dynamic allocation of cache buffer slots also includes determining availability of the storage buffer slot for the cache index as specified by the request. Upon determining the storage buffer slot is not available, the dynamic allocation of cache buffer slots includes evicting data stored in the storage buffer slot, and reserving the storage buffer slot for data associated with the request.

Abstract: A pipelined processing device includes: a processor configured to receive a request to perform an operation; a plurality of processing controllers configured to receive at least one instruction associated with the operation, each of the plurality of processing controllers including a memory to store at least one instruction therein; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor including shared error detection logic configured to detect a parity error in the at least one instruction as the at least one instruction is processed in a pipeline and generate an error signal; and a pipeline bus connected to each of the plurality of processing controllers and configured to communicate the error signal from the error detection logic.

Abstract: Dynamic pipeline cache error correction includes receiving a request to perform an operation that requires a storage cache slot, the storage cache slot residing in a cache. The dynamic pipeline cache error correction also includes accessing the storage cache slot, determining a cache hit for the storage cache slot, identifying and correcting any correctable soft errors associated with the storage cache slot. The dynamic cache error correction further includes updating the cache with results of corrected data.

Abstract: A method of managing a temporary memory includes: receiving a request to transfer data from a source location to a destination location, the data transfer request associated with an operation to be performed, the operation selected from an input into an intermediate temporary memory and an output; checking a two-state indicator associated with the temporary memory, the two-state indicator having a first state indicating that an immediately preceding operation on the temporary memory was an input to the temporary memory and a second state indicating that the immediately preceding operation was an output from the temporary memory; and performing the operation responsive to one of: the operation being an input operation and the two-state indicator being in the second state, indicating that the immediately preceding operation was an output; and the operation being an output operation and the two-state indicator being in the first state, indicating that the immediately preceding operation was an input.

Abstract: A system and method to organize and use data sent over a double data rate interface so that the system operation does not experience a time penalty. The first cycle of data is used independently of the second cycle so that latency is not jeopardized. There are many applications. In a preferred embodiment for an L2 cache, the system transmits congruence class data in the first half and can start to access the L2 cache directory with the congruence class data.

Abstract: Disclosed is a method and apparatus for arbitration between multiple pipelines over shared resources for an SMP computer system. The computer includes logic to defer arbitration until later in the pipeline to help reduce latency to each pipeline. Also, introduced is the concept of retry tags for better priority to avoid lock-out. The system also includes round-robin tokens to manage rejected requests to allow better fairness on conflicts. While the processing logic employed specifically applies to cross-interrogation, the logic can be extended to other common resources. The illustrated SMP computer system also has self-correcting logic to maintain good round-robin tokens.

Abstract: A double data rate interface in which the set-up interval is extended for a data path in which data is delayed relative to the other data path. Data is latched into a register comprised of mid cycle type latches, such as for example L2* latches. For example, if the delayed half of the data is not available until the second half of the double data rate cycle, the second half of the data is allowed to have a set-up interval around the mid cycle point while the on-chip timing logic launches the least delayed half of the data on the clock edge after it is set up, without waiting for the expiration of the set up interval of the delayed data.

Abstract: A system and method in which the receiving chip separately latches each half of the data received from the double data rate bus. Each half is launched as soon as it is available; one on the normal chip cycle time and the other is launched from a Master (L1) latch a half cycle into the normal chip cycle time. The first launched half of the data proceeds through the chip along its standard design chip path to be captured by the chips driving interface latch and launched again after one cycle of latency on the chip. The second half of the data proceeds through the chip one half cycle behind the first half, and is latched a half clock cycle later part way through the path into a Slave (L2) latch. On the next edge of the local clock, the data then continues from the L2 latch to the driving double data rate interface. This allows a half cycle set up time for the second half of the data so that it can be launched again, maintaining a one-cycle time on the chip.

Abstract: As a performance critical (high or full speed) request for a computer system data bus travels down a central pipeline, the system detects whether the interface data bus is currently empty or there is an ongoing half-speed transfer. If there is an ongoing low speed transfer, the system dynamically time shift or slows down the read rate out of the interleave buffer to half speed, and utilizes the free half of the bandwidth. This dynamic “zippering” or time shifting of data prevents a pipe pass from being rejected because the whole data bus is unavailable.

Abstract: As a performance critical (high or full speed) request for a computer system data bus travels down a central pipeline, the system detects whether the interface data bus is currently empty or there is an ongoing half-speed transfer. If there is an ongoing low speed transfer, the system dynamically time shift or slows down the read rate out of the interleave buffer to half speed, and utilizes the free half of the bandwidth. This dynamic “zippering” or time shifting of data prevents a pipe pass from being rejected because the whole data bus is unavailable.

Abstract: A computer system apparatus for asynchronous data transfer between a source and sink without the use of an asynchronous control signal. includes metastability circuits, data change detection logic, a stability window delay counter, and a mux/register pair to allow for the holding of previous stable data during the transition. While the processing logic employed specifically applies to asynchronous logic, the logic can be extended to synchronous or untimed interfaces as well. Also disclosed is a programmable means to adjust the window delay.

Abstract: A method and computer system apparatus for asynchronous data transfer between a source and sink without the use of an asynchronous control signal. includes metastability circuits, data change detection logic, a stability window delay counter, and a mux/register pair to allow for the holding of previous stable data during the transition. While the processing logic employed specifically applies to asynchronous logic, the logic can be extended to synchronous or untimed interfaces as well. Also disclosed is a programmable means to adjust the window delay.

Abstract: A method of forming a low AC loss, fully transposed cabled superconductor from multiple superconducting subconductors cut in a serpentine form from a wider superconducting tape is disclosed. By assembling pre-cut subconductor tapes a cable with a short transposition pitch length can be formed without excessive in-plane or out-of-plane deformation of the tape which could otherwise cause degradation of its superconducting performance. The transposition may be in either Roebel bar or Rutherford cable geometry.

Abstract: A method and computer system apparatus for asynchronous data transfer between a source and sink without the use of an asynchronous control signal. includes metastability circuits, data change detection logic, a stability window delay counter, and a mux/register pair to allow for the holding of previous stable data during the transition. While the processing logic employed specifically applies to asynchronous logic, the logic can be extended to synchronous or untimed interfaces as well. Also disclosed is a programmable means to adjust the window delay.

Abstract: Disclosed is a method and apparatus for arbitration between multiple pipelines over shared resources for an SMP computer system. The computer includes logic to defer arbitration until later in the pipeline to help reduce latency to each pipeline. Also, introduced is the concept of retry tags for better priority to avoid lock-out. The system also includes round-robin tokens to manage rejected requests to allow better fairness on conflicts. While the processing logic employed specifically applies to cross-interrogation, the logic can be extended to other common resources. The illustrated SMP computer system also has self-correcting logic to maintain good round-robin tokens.

Abstract: A double data rate interface in which the set-up interval is extended for a data path in which data is delayed relative to the other data path. Data is latched into a register comprised of mid cycle type latches, such as for example L2* latches. For example, if the delayed half of the data is not available until the second half of the double data rate cycle, the second half of the data is allowed to have a set-up interval around the mid cycle point while the on-chip timing logic launches the least delayed half of the data on the clock edge after it is set up, without waiting for the expiration of the set up interval of the delayed data.

Abstract: A system and method to organize and use data sent over a double data rate interface so that the system operation does not experience a time penalty. The first cycle of data is used independently of the second cycle so that latency is not jeopardized. There are many applications. In a preferred embodiment for an L2 cache, the system transmits congruence class data in the first half and can start to access the L2 cache directory with the congruence class data.

Abstract: A system and method in which the receiving chip separately latches each half of the data received from the double data rate bus. Each half is launched as soon as it is available; one on the normal chip cycle time and the other is launched from a Master (L1) latch a half cycle into the normal chip cycle time. The first launched half of the data proceeds through the chip along its standard design chip path to be captured by the chips driving interface latch and launched again after one cycle of latency on the chip. The second half of the data proceeds through the chip one half cycle behind the first half, and is latched a half clock cycle later part way through the path into a Slave (L2) latch. On the next edge of the local clock, the data then continues from the L2 latch to the driving double data rate interface. This allows a half cycle set up time for the second half of the data so that it can be launched again, maintaining a one-cycle time on the chip.