Abstract: A flat panel active electronically scanned array (AESA) (1) includes heterogeneous integrated circuit DC-DC voltage converters (3) periodically placed on array elements (2). A heterogeneous integrated circuit (100, 400, 500, 600) includes a voltage converter (101) configured to receive an input voltage (VI), and to convert the input voltage to an output voltage (VO) that is different from the input voltage, the voltage converter (101) comprising an analog and/or digital PWM circuit (104). The heterogeneous integrated circuit (100, 400, 500, 600) also includes a feedback circuit (103) configured to receive the output voltage (VO), and to generate a control signal used to vary a pulse width of a PWM signal generated by the analog and/or digital PWM circuit (104). The digital PWM circuit (104) is implemented in a heterogeneous integrated circuit (100, 400, 500, 600) fabricated on a common substrate (606) using CMOS and GaN fabrication processes.

Abstract: An antenna element includes a bias network circuitry for: during a receive mode, charging a transmit supply capacitor from a transmit power source while decoupling a receive supply capacitor from a receiver power source and coupling the receive supply capacitor to discharge and thereby provide bias to the receiver; and during a transmit mode, charging the receive supply capacitor from the receive power source while decoupling the transmit supply capacitor from the transmit power source and coupling the transmit supply capacitor to discharge and thereby provide bias the transmitter. The antenna element includes a phase shifter/attenuator section having an amplifier and a phase shifter and wherein bias voltage is provided to the amplifier and phase shifter by the transmit supply capacitor during the transmit mode and the receive supply capacitor during the receive mode.

Abstract: A feed structure for a radio frequency antenna, comprising: a plurality of radio frequency antenna elements; and a plurality of detectors, each one of the detectors being coupled to a corresponding one of the radio frequency antenna elements. Each one of the detectors is responsive to optical frequency energy to produce input radio frequency power for the corresponding one of the antenna elements coupled to said one of the detectors.

Abstract: An antenna element includes a bias network circuitry for: during a receive mode, charging a transmit supply capacitor from a transmit power source while decoupling a receive supply capacitor from a receiver power source and coupling the receive supply capacitor to discharge and thereby provide bias to the receiver; and during a transmit mode, charging the receive supply capacitor from the receive power source while decoupling the transmit supply capacitor from the transmit power source and coupling the transmit supply capacitor to discharge and thereby provide bias the transmitter.

Abstract: A digital to analog converter having a plurality of power dividers interconnected into a binary tree configuration, each one having an input and a pair of electrically isolated outputs for dividing power of an input signal at the input equally between the pair of outputs. A plurality of amplifiers is coupled between one of the pair of outputs of the one of the power dividers in one stage of the tree and the input of one of the power dividers in a succeeding stage of the tree. A power combiner is coupled between outputs of the amplifiers in a last one of the stages and an output of the analog to digital converter.

Abstract: A flat panel active electronically scanned array (AESA) (1) includes heterogeneous integrated circuit DC-DC voltage converters (3) periodically placed on array elements (2). A heterogeneous integrated circuit (100, 400, 500, 600) includes a voltage converter (101) configured to receive an input voltage (VI), and to convert the input voltage to an output voltage (VO) that is different from the input voltage, the voltage converter (101) comprising an analog and/or digital PWM circuit (104). The heterogeneous integrated circuit (100, 400, 500, 600) also includes a feedback circuit (103) configured to receive the output voltage (VO), and to generate a control signal used to vary a pulse width of a PWM signal generated by the analog and/or digital PWM circuit (104). The digital PWM circuit (104) is implemented in a heterogeneous integrated circuit (100, 400, 500, 600) fabricated on a common substrate (606) using CMOS and GaN fabrication processes.

Abstract: A digital to analog converter having a plurality of power dividers interconnected into a binary tree configuration, each one having an input and a pair of electrically isolated outputs for dividing power of an input signal at the input equally between the pair of outputs. A plurality of amplifiers is coupled between one of the pair of outputs of the one of the power dividers in one stage of the tree and the input of one of the power dividers in a succeeding stage of the tree. A power combiner is coupled between outputs of the amplifiers in a last one of the stages and an output of the analog to digital converter.

Abstract: A feed structure for a radio frequency antenna, comprising: a plurality of radio frequency antenna elements; and a plurality of detectors, each one of the detectors being coupled to a corresponding one of the radio frequency antenna elements. Each one of the detectors is responsive to optical frequency energy to produce input radio frequency power for the corresponding one of the antenna elements coupled to said one of the detectors.

Abstract: A method for packaging a semiconductor device. The method includes: providing a dielectric layer over the semiconductor device; determining patterns and placement of material on the dielectric layer to provide a predetermined magnetic or electric effect for the device, such effects being provided on the device from such patterned and placed material solely by electrical or magnetic waves coupled between such material and the device; and forming the material in the determined patterns and placement to provide the predetermined effects.

Abstract: A system for detecting the amplitude of radio frequency energy includes: an antenna for receiving the radio frequency energy; a modulator, responsive to a reference frequency signal, for pulse modulating the received radio frequency energy at the reference frequency; a detector for converting such pulse modulated signal to a detector output signal having a low frequency component representative of the amplitude of the received radio frequency energy, in summation with DC bias current, and a high frequency component at the reference signal; and a high pass or band pass filter fed for the detector output signal for passing the high frequency components and for removing the low frequency component. A phase detector, with or without a subsequent IF amplifier, is fed by the reference frequency and the high frequency components for producing an output representative of the high frequency components.

Abstract: A method for packaging a semiconductor device. The method includes: providing a dielectric layer over the semiconductor device; determining patterns and placement of material on the dielectric layer to provide a predetermined magnetic or electric effect for the device, such effects being provided on the device from such patterned and placed material solely by electrical or magnetic waves coupled between such material and the device; and forming the material in the determined patterns and placement to provide the predetermined effects.

Abstract: A method for packaging a semiconductor device. The method includes: providing a dielectric layer over the semiconductor device; determining patterns and placement of material on the dielectric layer to provide a predetermined magnetic or electric effect for the device, such effects being provided on the device from such patterned and placed material solely by electrical or magnetic waves coupled between such material and the device; and forming the material in the determined patterns and placement to provide the predetermined effects.

Abstract: A system for detecting the amplitude of radio frequency energy includes: an antenna for receiving the radio frequency energy; a modulator, responsive to a reference frequency signal, for pulse modulating the received radio frequency energy at the reference frequency; a detector for converting such pulse modulated signal to a detector output signal having a low frequency component representative of the amplitude of the received radio frequency energy, in summation with DC bias current, and a high frequency component at the reference signal; and a high pass or band pass filter fed for the detector output signal for passing the high frequency components and for removing the low frequency component. A phase detector, with or without a subsequent IF amplifier, is fed by the reference frequency and the high frequency components for producing an output representative of the high frequency components.

Abstract: A circuit having a frequency controllable oscillator and a variable time delay circuit. The time delay circuit is fed by a signal produced by the oscillator, such time delay circuit being coupled to the oscillator to control the frequency of the signal produced by the oscillator. The circuit allows frequency agility of a phase locked loop although locked to a common reference frequency.

Abstract: A semiconductor structure having: a III-V substrate structure; an enhancement mode transistor device disposed in a first region of the structure; a depletion mode transistor device disposed in a laterally displaced second region of the structure; and a RF/microwave/milli-meter wave transistor device formed in a laterally displaced third region thereof.

Abstract: A method for packaging a plurality of semiconductor devices formed in a surface portion of a semiconductor wafer. The method includes: lithographically forming in a material disposed on the surface portion of the semiconductor wafer device-exposing openings to exposed the devices and electrical contacts pads openings to expose electrical contact pads for devices; mounting a rigid dielectric layer over the formed material, such rigid material being suspended over the device exposing openings in the material and over the electrical contacts pads openings in the material; and forming electrical contact pad openings in portions of the rigid dielectric layer disposed over electrical contact pads of the devices with other portions of the rigid dielectric layer remaining suspended over the device exposing openings in the material.

Abstract: A method for packaging a semiconductor device. The method includes: providing a dielectric layer over the semiconductor device; determining patterns and placement of material on the dielectric layer to provide a predetermined magnetic or electric effect for the device, such effects being provided on the device from such patterned and placed material solely by electrical or magnetic waves coupled between such material and the device; and forming the material in the determined patterns and placement to provide the predetermined effects.

Abstract: A method includes providing a single crystal wafer having MMIC chips. Each chip has an active device in a first surface portion of a semiconductor substrate provided by the wafer and an electrical interconnect having a first portion disposed on a second surface of the semiconductor substrate. The semiconductor substrate structure has a via therethrough, a second portion of the electrical interconnect passing though the via and being electrically connected to the active device. A multilayer interconnect structure is formed on the wafer providing a signal routing section on the second surface portion of a corresponding one of the chips. Each section has dielectric layers and an electrical conductor, such electrical conductor being electrically coupled to the active device to route an electrical signal to such active device. Each chip and the corresponding signal routing section are separated from the wafer.

Abstract: A circuit having a frequency controllable oscillator and a variable time delay circuit. The time delay circuit is fed by a signal produced by the oscillator, such time delay circuit being coupled to the oscillator to control the frequency of the signal produced by the oscillator. The circuit allows frequency agility of a phase locked loop although locked to a common reference frequency.

Abstract: A phase shifter is fed an input signal having a frequency f. A coupler is included fed by the input signal. The coupler has a pair of output terminals for providing a pair of signals having the frequency f and having a relative phase shift difference of m?/2 radians, where m is an integer. A switch is included having a pair of inputs, each one of the pair of inputs being coupled to a corresponding one of the pair of output terminals of the coupler. The switch has an output, one of the pair of inputs of the switch being coupled to the output of the switch selectively in accordance with a first control signal fed to the switch.