Patents by Inventor Michael G. Miller

Michael G. Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11393548
    Abstract: In one embodiment, a system maintains metadata associating each block of a plurality of blocks of the memory device with a corresponding frequency access group, where each frequency access group is associated with a corresponding scan frequency. The system determines that a first predetermined time period has elapsed since a last scan operation performed with respect to one or more blocks of the memory device, where the first predetermined time period specifies a first scan frequency. The system selects, based on the metadata, at least one block from a first frequency access group associated with the first scan frequency. The system performs a scan operation with respect to the selected block.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Renato C. Padilla, Sampath K. Ratnam, Christopher M. Smitchger, Vamsi Pavan Rayaprolu, Gary F. Besinga, Michael G. Miller, Tawalin Opastrakoon
  • Publication number: 20220199179
    Abstract: In one embodiment, a system maintains metadata associating each block of a plurality of blocks of the memory device with a corresponding frequency access group, where each frequency access group is associated with a corresponding scan frequency. The system determines that a first predetermined time period has elapsed since a last scan operation performed with respect to one or more blocks of the memory device, where the first predetermined time period specifies a first scan frequency. The system selects, based on the metadata, at least one block from a first frequency access group associated with the first scan frequency. The system performs a scan operation with respect to the selected block.
    Type: Application
    Filed: December 18, 2020
    Publication date: June 23, 2022
    Inventors: Renato C. Padilla, Sampath K. Ratnam, Christopher M. Smitchger, Vamsi Pavan Rayaprolu, Gary F. Besinga, Michael G. Miller, Tawalin Opastrakoon
  • Patent number: 11366592
    Abstract: An asynchronous power loss (APL) event is detected at a memory device. A last written page is identified in the memory device in response to detecting the APL event. A count of zeros programmed in the last written page is determined. The count of zeros is compared to a threshold constraint to determine whether to perform a dummy write operation on the last written page.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: June 21, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Michael G. Miller, Gary F. Besigna
  • Publication number: 20220188226
    Abstract: An amount of threshold voltage distribution shift is determined. The threshold voltage distribution shift corresponds to an amount of time after programming of a reference page of a block of a memory device. A program-verify voltage is adjusted based on the amount of threshold voltage distribution shift to obtain an adjusted program-verify voltage. Using the adjusted program-verify voltage, a temporally subsequent page of the block is programmed at a time corresponding to the amount of time after the programming of the reference page.
    Type: Application
    Filed: December 16, 2020
    Publication date: June 16, 2022
    Inventors: Gary F. Besinga, Renato C. Padilla, Tawalin Opastrakoon, Sampath K. Ratnam, Michael G. Miller, Christopher M. Smitchger, Vamsi Pavan Rayaprolu, Ashutosh Malshe
  • Patent number: 11361833
    Abstract: Several embodiments of memory devices and systems with offset memory component automatic calibration error recovery are disclosed herein. In one embodiment, a system includes at least one memory region and calibration circuitry. The memory region has memory cells that read out data states in response to application of a current read level signal. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to one or more of a plurality of offset read level test signals, including a base offset read level test signal. The base offset read level test signal is offset from the current read level signal by a predetermined value. The calibration circuitry is further configured to output the determined read level offset value.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: June 14, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Gerald L. Cadloni, Gary F. Besinga, Michael G. Miller, Renato C. Padilla
  • Publication number: 20220129187
    Abstract: A processing device detects a read operation at a memory device that is directed at a word line group from among multiple word line groups of the memory device. The processing device increments a read counter associated with the word line group based on the read operation being directed at the word line group. The processing device determines the read counter exceeds a read-disturb threshold and performs read-disturb handling on the word line group in response to determining the read counter exceeds the read-disturb threshold.
    Type: Application
    Filed: October 26, 2020
    Publication date: April 28, 2022
    Inventors: Michael G. Miller, Ashutosh Malshe, Gianni Stephen Alsasua, Renato Padilla, JR., Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Harish Reddy Singidi
  • Publication number: 20220091740
    Abstract: Memory devices are disclosed. A memory device may include dynamic cache, static cache, and a memory controller. The memory controller may be configured to disable the static cache responsive to a number of program/erase (PE) cycles consumed by the static cache being greater than an endurance of the static cache. The memory controller may also be configured to disable the dynamic cache responsive to a number of PE cycles consumed by the dynamic cache being greater than an endurance of the dynamic cache. Associated methods and systems are also disclosed.
    Type: Application
    Filed: December 3, 2021
    Publication date: March 24, 2022
    Inventors: Kishore K. Muchherla, Ashutosh Malshe, Sampath k. Ratnam, Peter Feeley, Michael G. Miller, Christopher S. Hale, Renato C. Padilla
  • Publication number: 20220066650
    Abstract: An asynchronous power loss (APL) event is detected at a memory device. A last written page is identified in the memory device in response to detecting the APL event. A count of zeros programmed in the last written page is determined. The count of zeros is compared to a threshold constraint to determine whether to perform a dummy write operation on the last written page.
    Type: Application
    Filed: August 31, 2020
    Publication date: March 3, 2022
    Inventors: Michael G. Miller, Gary F. Besinga
  • Publication number: 20220066651
    Abstract: An asynchronous power loss (APL) event is detected at a memory device. An APL affected page is identified in the memory device in response to detecting the APL event. A dummy write operation is performed to write dummy data to the APL affected page using an enhanced programming sequence with a reduced pulse count to reduce program disturb errors on neighboring pages.
    Type: Application
    Filed: August 31, 2020
    Publication date: March 3, 2022
    Inventors: Michael G. Miller, Gary F. Besinga
  • Patent number: 11250918
    Abstract: Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: February 15, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Ashutosh Malshe, Harish Reddy Singidi, Kishore Kumar Muchherla, Michael G. Miller, Sampath Ratnam, Xu Zhang, Jie Zhou
  • Publication number: 20220013182
    Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.
    Type: Application
    Filed: September 24, 2021
    Publication date: January 13, 2022
    Inventors: Kishore K. Muchherla, Ashutosh Malshe, Preston A. Thomson, Michael G. Miller, Gary F. Besinga, Scott A. Stoller, Sampath K. Ratnam, Renato C. Padilla, Peter Feeley
  • Patent number: 11204696
    Abstract: Memory devices including a hybrid cache, methods of operating a memory device, and associated electronic systems including a memory device having a hybrid cache, are disclosed. The hybrid cache includes a dynamic cache that may include x-level cell (XLC) blocks of non-volatile memory cells, which may include multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), etc., shared between the dynamic cache and a main memory. The hybrid cache includes a static cache including single-level cell (SLC) blocks of non-volatile memory cells. The memory device further includes a memory controller configured to disable at least one of the static cache and the dynamic cache based on a workload of the hybrid cache relative to a Total Bytes Written (TBW) Spec for the memory device. The cache may be disabled based on, for example, program/erase (PE) cycles of one or more portions of the memory device or the workload exceeding a threshold, which may define one or more switch points.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: December 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Ashutosh Malshe, Sampath K. Ratnam, Peter Feeley, Michael G. Miller, Christopher S. Hale, Renato C. Padilla
  • Publication number: 20210365184
    Abstract: The occurrence of an asynchronous power loss (APL) event is detected in a memory sub-system. In response, an APL handling operation is performed. The APL handing operation includes identifying a last written page at a first page location in a block of the memory device, wherein the last written page is associated with a memory cell of the memory device, copying data from the last written page and from a related page associated with the memory cell to a temporary storage area in the memory device, copying the data from the temporary storage area to a second page location in the block of the memory device, and providing a notification that the memory device has recovered from the APL event.
    Type: Application
    Filed: August 4, 2021
    Publication date: November 25, 2021
    Inventor: Michael G. Miller
  • Patent number: 11158392
    Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Ashutosh Malshe, Preston A. Thomson, Michael G. Miller, Gary F. Besinga, Scott A. Stoller, Sampath K. Ratnam, Renato C. Padilla, Peter Feeley
  • Publication number: 20210286525
    Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.
    Type: Application
    Filed: May 27, 2021
    Publication date: September 16, 2021
    Inventors: Kishore K. Muchherla, Ashutosh Malshe, Preston A. Thomson, Michael G. Miller, Sampath K. Ratnam, Renato C. Padilla, Peter Feeley
  • Patent number: 11120885
    Abstract: An indication of an initialization of power to a memory device is received. Responsive to receiving the indication of the initialization of power to the memory device, whether a status indicator associated with a written page of the memory device can be read is determined. Responsive to determining that the status indicator cannot be read, a programming of data to the memory device did not complete based on a prior loss of power to the memory device is determined.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michael G. Miller, Kishore Kumar Muchherla, Harish R. Singidi, Walter Di Francesco, Renato C. Padilla, Gary F. Besinga, Violante Moschiano
  • Patent number: 11106372
    Abstract: An asynchronous power loss (APL) event is determined to occur. A first erased page (FEP) in a block of a memory device is determined and a last written page (LWP) is determined from the FEP. Data is read from the LWP and peer pages corresponding to the LWP. The data is copied to a temporary area in the memory device and a write pointer is incremented by a deterministic number of pages in the block. Data from the temporary area is copied to a page location in the block identified by the write pointer and the write pointer is incremented by the deterministic number of pages again. A host system is notified that the memory device is ready for a subsequent programming operation after the APL event.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Michael G. Miller
  • Publication number: 20210264991
    Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.
    Type: Application
    Filed: May 12, 2021
    Publication date: August 26, 2021
    Inventors: Harish Singidi, Kishore Kumar Muchherla, Gianni Stephen Alsasua, Ashutosh Malshe, Sampath Ratnam, Gary F. Besinga, Michael G. Miller
  • Publication number: 20210232508
    Abstract: An example method of the present disclosure includes, responsive to a loss of last written page information by a memory system, initiating a last written page search to determine last written page information of a memory device, where the last written page search is initiated via a command from a controller of the memory system to the memory device, responsive to receiving the command, performing the last written page search on the memory device, and providing the last written page information to the controller.
    Type: Application
    Filed: April 12, 2021
    Publication date: July 29, 2021
    Inventors: Dheeraj Srinivasan, Ali Mohammadzadeh, Michael G. Miller, Xiaoxiao Zhang, Jung Sheng Hoei
  • Publication number: 20210200435
    Abstract: An asynchronous power loss (APL) event is determined to occur. A first erased page (FEP) in a block of a memory device is determined and a last written page (LWP) is determined from the FEP. Data is read from the LWP and peer pages corresponding to the LWP. The data is copied to a temporary area in the memory device and a write pointer is incremented by a deterministic number of pages in the block. Data from the temporary area is copied to a page location in the block identified by the write pointer and the write pointer is incremented by the deterministic number of pages again. A host system is notified that the memory device is ready for a subsequent programming operation after the APL event.
    Type: Application
    Filed: May 27, 2020
    Publication date: July 1, 2021
    Inventor: Michael G. Miller