Abstract: A method for detecting a code word is proposed, wherein the code word is a code word of one of at least two codes, wherein n states are read from memory cells of a memory, respectively. The n states are determined in a time domain for each of the at least two codes, wherein additionally n states are read from further memory cells and at least one reference value is determined therefrom and wherein the at least one reference value is taken as a basis for determining which of the at least two codes is the correct code. A corresponding device is furthermore specified.

Abstract: In an embodiment, a storage device includes a multiplicity of data value memory cells and a multiplicity of check value memory cells, where at least one of the multiplicity of data value memory cells is assigned to two of the check value memory cells, and where at least one of the multiplicity of check value memory cells is assigned to two of the data value memory cells, and a correction circuit which is configured to output a corrected data value when reading out a selected data value memory cell of the at least one of the multiplicity of data value memory cells, based on a content of the selected data value memory cell and based on contents of the two check value memory cells assigned to the selected data value memory cell.

Abstract: A solution is proposed for processing data bits, in which the data bits are transformed into first data bytes by means of a first transformation, in which the first data bytes are stored in a memory, in which second data bytes are read from the memory, in which each of the second data bytes, when there is no error, is a codeword of a block error code and in which one error signal per second data byte is determined that indicates whether or not this second data byte is a codeword.

Abstract: A method for detecting an address error when reading a bitstream from a memory is proposed, wherein a check is carried out as to whether the bitstream in conjunction with the present read address is a code word of an error code and wherein, should the bitstream in conjunction with the present read address not be a code word of the error code, an address error is subsequently detected provided the error code does not correct an error correctable thereby. Accordingly, an apparatus, a system and a computer program product are specified.

Abstract: A method for detecting a code word is proposed, wherein the code word is a code word of one of at least two codes, wherein n states are read from memory cells of a memory, respectively. The n states are determined in a time domain for each of the at least two codes, wherein additionally n states are read from further memory cells and at least one reference value is determined therefrom and wherein the at least one reference value is taken as a basis for determining which of the at least two codes is the correct code. A corresponding device is furthermore specified.

Abstract: A circuit arrangement for determining in parallel of at least two byte error position signals for identifying at least one byte error in a binary sequence comprising a plurality of bytes, wherein the binary sequence in the error-free case is a code word of an error code, the circuit arrangement is configured such that each of the at least two byte error position signals is determinable using components of an error syndrome of the error code such that the components indicate whether or not a byte of the binary sequence that is associated with the byte error position signal is erroneous.

Abstract: What is specified is a method for transforming a first binary signal read from a memory, wherein the first binary signal is transformed into a second binary signal provided that the first binary signal is a code word or a predefined code word of a k-out-of-n code, wherein the first binary signal is transformed into a predefined signal provided that the first binary signal is not a code word or is not a predefined code word of the k-out-of-n code, wherein the predefined signal is different than the second binary signal. A corresponding device is furthermore specified.

Abstract: A determination is made that error-correcting code functionality detected a first number of erroneous bits within a memory device. Bits within the memory device are evaluated to identify a subset of the bits as candidate bits. The candidate bits are evaluated to determine whether the error-correcting code functionality returns a non-error state, where no error correction is performed, based upon one or more combinations of candidate bits being inverted. Responsive to the error-correcting code functionality returning the non-error state for only one combination of the one or more combinations of candidate bits being inverted, the one combination of candidate bits is corrected.

Abstract: A method and associated apparatus is disclosed for processing data by means of an error code, wherein the error code has an H-matrix with n columns and m rows, wherein the columns of the H-matrix are different, wherein component-by-component XOR sums of adjacent columns of the H-matrix are different from one another and from all columns of the H-matrix and wherein component-by-component XOR sums of nonadjacent columns of the H-matrix are different from all columns of the H-matrix and from all component-by-component XOR sums of adjacent columns of the H-matrix.

Abstract: A circuit arrangement for determining a correction signal on the basis of at least one bit error of a binary word is specified, including a plurality of subcircuits (ST), wherein a respective subcircuit is provided for a bit position to be corrected of the binary word, wherein each of the subcircuits provides at least two locator polynomial values, and comprising a selection unit, which determines a correction signal depending on the locator polynomial values and depending on an error signal (err, E). A method for driving such a circuit arrangement is furthermore proposed.

Abstract: A method for compensating for a read error is disclosed, wherein each of n states are read from memory cells of a memory, the states being determined in a time domain. If the n states do not form a code word of a k-from-n code, a plurality of states from the n states, which were determined within a reading window, are provided with a first valid assignment and fed to an error processing stage. If the error processing does not indicate an error, the n states are further processed with the first valid assignment, and if the error processing indicates an error, the plurality of states that were determined within the reading window are provided with a second valid assignment and the n states are further processed with the second valid assignment. Accordingly, a device, a system and a computer program product are also disclosed.

Abstract: The disclosure proposes a circuit including a memory which has a multiplicity of memory cells, the memory having a first area and a second area, at least one memory cell comprising a part of the first area and a part of the second area, the first area having a lower reliability than the second area, and the circuit being set up in such a manner that first bits are stored in the first area and second bits are stored in the second area. A circuit for reading the memory and methods for writing to and reading the memory are also disclosed.

Abstract: A method is proposed for processing a data word, in which the data word comprises a first partial data word and a second partial data word, in which first checkbits are defined for the first partial data word, wherein the first partial data word and the first checkbits form a first codeword, in which second checkbits are defined for the second partial data word, wherein the second partial data word and the second checkbits form a second codeword, in which third checkbits are defined for the data word, wherein at least (i) the data word, (ii) a linking of the first checkbits with the second checkbits, and (iii) the third checkbits are parts of a third codeword.

Abstract: A method for reading memory cells from a memory is stated, inter alia, in which physical values are determined from a number of n memory cells, wherein n is at least three, in which the physical values are at least partially compared with one another, in which K different digital memory cell values are assigned to the n memory cells on the basis of the compared physical values, and in which a code word of an n1-, . . . , nK-out-of-n code is assigned to the digital memory cell values obtained in this manner. In particular, the following apply in this case: n?3, n1?1 to nK?1, K?2 and m?1.

Abstract: The disclosure proposes a circuit including a memory which has a multiplicity of memory cells, the memory having a first area and a second area, at least one memory cell comprising a part of the first area and a part of the second area, the first area having a lower reliability than the second area, and the circuit being set up in such a manner that first bits are stored in the first area and second bits are stored in the second area. A circuit for reading the memory and methods for writing to and reading the memory are also disclosed.

Abstract: A solution is proposed for processing data bits, in which the data bits are transformed into first data bytes by means of a first transformation, in which the first data bytes are stored in a memory, in which second data bytes are read from the memory, in which each of the second data bytes, when there is no error, is a codeword of a block error code and in which one error signal per second data byte is determined that indicates whether or not this second data byte is a codeword.

Abstract: A circuit arrangement for determining in parallel of at least two byte error position signals for identifying at least one byte error in a binary sequence comprising a plurality of bytes, wherein the binary sequence in the error-free case is a code word of an error code, the circuit arrangement is configured such that each of the at least two byte error position signals is determinable using components of an error syndrome of the error code such that the components indicate whether or not a byte of the binary sequence that is associated with the byte error position signal is erroneous.

Abstract: In various embodiments, a method of correcting and/or detecting an error in a memory device is provided. The method may include, in a first operations mode, applying a first code to detect and/or correct an error, and in a second operations mode after an inactive mode and before entering the first operations mode, applying a second code for correcting and/or detecting an error, wherein the first code and the second code have different code words.

Abstract: An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence.

Abstract: In various embodiments, a method of using a memory device is provided. The method may include storing data units, check units of a first code and check units of a second code in memory cells of the memory device, wherein the data units and the check units of the first code form code words of the first code, and wherein the data units and the check units of the second code form code words of the second code, applying the second code for error correction in at least a portion of the data units and/or in at least a portion of the check units of the first code, after the correcting the errors, retaining at least a retaining portion of the data units and of the check units of the first code and deleting at least a deleting portion of the check units of the second code, thereby freeing the memory cells that are occupied by the deleting portion of the check units of the second code, and during a subsequent using of the memory device, storing data in at least a reuse portion of the freed-up memory cells.