Patents by Inventor Michael Goessel
Michael Goessel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240146333Abstract: An approach to correcting errors in a string of symbols is proposed, in which the string of symbols is transformed by a transformation ? into a first group of symbols and into a second group of symbols, and in which the group of symbols that has fewer erroneous symbols than the other group is corrected using a first error code.Type: ApplicationFiled: October 16, 2023Publication date: May 2, 2024Inventors: Thomas Kern, Michael Goessel
-
Publication number: 20240126640Abstract: A method for storing data bits in memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are stored in the memory cells. A method for reading data bits from memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are read from the memory cells based on the coded predefined functionality. Corresponding apparatuses and memories are also disclosed.Type: ApplicationFiled: December 20, 2023Publication date: April 18, 2024Inventors: Thomas Kern, Thomas Rabenalt, Michael Goessel
-
Publication number: 20240048159Abstract: What is proposed is a solution for processing errors in a sequence of bits, wherein the sequence of bits, in the error-free case, forms a codeword of an error code, wherein the error code is based on an H-matrix or is able to be determined thereby, wherein an error syndrome is determined for the sequence of bits, wherein a link is determined between components of the error syndrome and parts of the H-matrix, and wherein two adjacent bits in the sequence of bits are corrected if the link adopts a predefined value.Type: ApplicationFiled: July 20, 2023Publication date: February 8, 2024Inventors: Jens Rosenbusch, Klaus Oberländer, Georg Duchrau, Michael Goessel
-
Patent number: 11892906Abstract: A method for storing data bits in memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are stored in the memory cells. A method for reading data bits from memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are read from the memory cells based on the coded predefined functionality. Corresponding apparatuses and memories are also disclosed.Type: GrantFiled: August 3, 2021Date of Patent: February 6, 2024Assignee: Infineon Technologies AGInventors: Thomas Kern, Thomas Rabenalt, Michael Goessel
-
Patent number: 11861184Abstract: A method for determining a resultant data word when accessing memory cells includes reading a set of memory cells, and determining first and second data words therefrom. Each memory cell is assigned a component of the first and second data words. The first and second data words for the respective memory cell assume a first value if a first comparison with a first reference value and a second comparison with a second reference value show that the two reference values are greater and assume a second value if the first comparison with the first reference value and the second comparison with the second reference value show that the two reference values are smaller. The first and second data words assume at least one third value if neither condition is satisfied. The resultant data word is determined based on the first or second data words. A corresponding device is also proposed.Type: GrantFiled: September 13, 2022Date of Patent: January 2, 2024Assignee: Infineon Technologies AGInventors: Thomas Kern, Michael Goessel
-
Publication number: 20230267039Abstract: A solution is proposed for error processing, wherein n byte error positions of n byte errors are predefined (where n is a positive integer), wherein this involves determining whether there is a further byte error position on the basis of the n byte error positions and on the basis of n + 1 error syndrome components of a first error code.Type: ApplicationFiled: January 25, 2023Publication date: August 24, 2023Inventors: Thomas Kern, Michael Goessel, Alexander Klockmann, Thomas Rabenalt
-
Patent number: 11722153Abstract: Processing of a bit sequence is proposed, wherein (i) a first partial error syndrome s1 of an error syndrome and a second partial error syndrome s2 of the error syndrome are determined for the bit sequence, (ii) a first comparison value is determined on the basis of a bit position and the first partial error syndrome, (iii) a second comparison value is determined on the basis of the bit position and the second partial error syndrome, and (iv) the bit position is corrected should a comparison of the first comparison value with the second comparison value assume a specified value and otherwise the bit position is not corrected.Type: GrantFiled: January 20, 2022Date of Patent: August 8, 2023Assignee: Infineon Technologies AGInventors: Thomas Kern, Michael Goessel, Thomas Rabenalt
-
Patent number: 11650877Abstract: A method for detecting an address error when reading a bitstream from a memory is proposed, wherein a check is carried out as to whether the bitstream in conjunction with the present read address is a code word of an error code and wherein, should the bitstream in conjunction with the present read address not be a code word of the error code, an address error is subsequently detected provided the error code does not correct an error correctable thereby. Accordingly, an apparatus, a system and a computer program product are specified.Type: GrantFiled: May 22, 2020Date of Patent: May 16, 2023Assignee: Infineon Technologies AGInventors: Thomas Kern, Klaus Oberlaender, Christian Badack, Michael Goessel
-
Publication number: 20230095070Abstract: A method for determining a resultant data word when accessing memory cells includes reading a set of memory cells, and determining first and second data words therefrom. Each memory cell is assigned a component of the first and second data words. The first and second data words for the respective memory cell assume a first value if a first comparison with a first reference value and a second comparison with a second reference value show that the two reference values are greater and assume a second value if the first comparison with the first reference value and the second comparison with the second reference value show that the two reference values are smaller. The first and second data words assume at least one third value if niether condition is satisfied. The resultant data word is determined based on the first or second data words. A corresponding device is also proposed.Type: ApplicationFiled: September 13, 2022Publication date: March 30, 2023Inventors: Thomas Kern, Michael Goessel
-
Publication number: 20230091457Abstract: An approach for correcting at least one byte error in a binary sequence is proposed, the binary sequence comprising a plurality of bytes and being a code word of an error code in the error-free case. The approach comprises the steps of: (i) determining at least one byte error position signal which specifies whether or not a byte of the binary sequence is erroneous, (ii) determining at least one byte error correction value, based on which an erroneous byte position identified by means of the byte error position signal is correctable, the at least one byte error correction value being determined by virtue of a first value and a second value being determined for each of at least two byte positions based on a coefficient of the locator polynomial, and (iii) correcting the at least one byte error based on the at least one byte error correction value.Type: ApplicationFiled: September 14, 2022Publication date: March 23, 2023Inventors: Thomas Kern, Thomas Rabenalt, Michael Goessel
-
Patent number: 11556412Abstract: A method and associated apparatus is disclosed for processing data by means of an error code, wherein the error code has an H-matrix with n columns and m rows, wherein the columns of the H-matrix are different, wherein component-by-component XOR sums of adjacent columns of the H-matrix are different from one another and from all columns of the H-matrix and wherein component-by-component XOR sums of nonadjacent columns of the H-matrix are different from all columns of the H-matrix and from all component-by-component XOR sums of adjacent columns of the H-matrix.Type: GrantFiled: October 25, 2019Date of Patent: January 17, 2023Assignee: Infineon Technologies AGInventors: Christian Badack, Jessica Trebst, Michael Goessel, Klaus Oberlaender
-
Publication number: 20220345157Abstract: A solution for detecting a multibyte error in a code word of a shortened error code is proposed, the shortened error code is a ?-byte-correcting error code, wherein bytes of the code word of the shortened error code determined a first range, the non-correctable multibyte error is detected if at least one of the following conditions is met: (a) at least one error position signal does not lie in the first range; (b) at least one error position signal indicates at least one error but fewer than terrors in the first range and no 1-byte error to (??1)-byte error is present.Type: ApplicationFiled: April 13, 2022Publication date: October 27, 2022Inventors: Thomas Kern, Michael Goessel, Alexander Klockmann, Thomas Rabenalt
-
Patent number: 11455104Abstract: Method for determining a resultant data word when accessing memory cells of a memory, comprising the steps: (a) reading a set of memory cells, (b) wherein a first data word and a second data word are determined from the read set of memory cells, wherein each memory cell is assigned a component of the first data word and the corresponding component of the second data word, (c) wherein the first data word and the second data word for the respective memory cell assume a first value if a first comparison with a first reference value and a second comparison with a second reference value show that the two reference values are greater and assume a second value if the first comparison with the first reference value and the second comparison with the second reference value show that the two reference values are smaller, (d) wherein the first data word and the second data word for the respective memory cell assume at least one third value if the conditions according to feature (c) are not satisfied, and (e) determiningType: GrantFiled: January 8, 2021Date of Patent: September 27, 2022Assignee: Infineon Technologies AGInventors: Thomas Kern, Michael Goessel
-
Publication number: 20220231704Abstract: Processing of a bit sequence is proposed, wherein (i) a first partial error syndrome s1 of an error syndrome and a second partial error syndrome s2 of the error syndrome are determined for the bit sequence, (ii) a first comparison value is determined on the basis of a bit position and the first partial error syndrome, (iii) a second comparison value is determined on the basis of the bit position and the second partial error syndrome, and (iv) the bit position is corrected should a comparison of the first comparison value with the second comparison value assume a specified value and otherwise the bit position is not corrected.Type: ApplicationFiled: January 20, 2022Publication date: July 21, 2022Inventors: Thomas Kern, Michael Goessel, Thomas Rabenalt
-
Patent number: 11362684Abstract: A method for detecting a code word is proposed, wherein the code word is a code word of one of at least two codes, wherein n states are read from memory cells of a memory, respectively. The n states are determined in a time domain for each of the at least two codes, wherein additionally n states are read from further memory cells and at least one reference value is determined therefrom and wherein the at least one reference value is taken as a basis for determining which of the at least two codes is the correct code. A corresponding device is furthermore specified.Type: GrantFiled: March 4, 2021Date of Patent: June 14, 2022Assignee: Infineon Technologies AGInventors: Thomas Kern, Michael Goessel
-
Patent number: 11327835Abstract: In an embodiment, a storage device includes a multiplicity of data value memory cells and a multiplicity of check value memory cells, where at least one of the multiplicity of data value memory cells is assigned to two of the check value memory cells, and where at least one of the multiplicity of check value memory cells is assigned to two of the data value memory cells, and a correction circuit which is configured to output a corrected data value when reading out a selected data value memory cell of the at least one of the multiplicity of data value memory cells, based on a content of the selected data value memory cell and based on contents of the two check value memory cells assigned to the selected data value memory cell.Type: GrantFiled: July 31, 2020Date of Patent: May 10, 2022Assignee: INFINEON TECHNOLOGIES AGInventors: Georg Georgakos, Michael Goessel
-
Patent number: 11262948Abstract: What is specified is a method for transforming a first binary signal read from a memory, wherein the first binary signal is transformed into a second binary signal provided that the first binary signal is a code word or a predefined code word of a k-out-of-n code, wherein the first binary signal is transformed into a predefined signal provided that the first binary signal is not a code word or is not a predefined code word of the k-out-of-n code, wherein the predefined signal is different than the second binary signal. A corresponding device is furthermore specified.Type: GrantFiled: March 17, 2020Date of Patent: March 1, 2022Assignee: Infineon Technologies AGInventors: Thomas Kern, Michael Goessel, Thomas Rabenalt
-
Publication number: 20220044753Abstract: A method for storing data bits in memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are stored in the memory cells. A method for reading data bits from memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are read from the memory cells based on the coded predefined functionality. Corresponding apparatuses and memories are also disclosed.Type: ApplicationFiled: August 3, 2021Publication date: February 10, 2022Inventors: Thomas Kern, Thomas Rabenalt, Michael Goessel
-
Patent number: 11182246Abstract: Systems, methods, and circuitries are disclosed for protecting data throughout read and write operations. In one example a method includes receiving a plurality of data bits; dividing the plurality of data bits into at least two data blocks; generating respective sets of block check bits for each respective data block using a respective first error code; combining the sets of block check bits to generate a set of signature bits for the plurality of data bits; generating a set of cumulative check bits for the plurality of data bits and the set of signature bits using a second error code; and storing, in a memory location, the plurality of data bits, the set of signature bits, and the set of cumulative check bits.Type: GrantFiled: July 28, 2020Date of Patent: November 23, 2021Assignee: Infineon Technologies AGInventors: Thomas Kern, Christian Badack, Michael Goessel, Klaus Oberlaender
-
Patent number: 11157352Abstract: A method for compensating for a read error is disclosed, wherein each of n states are read from memory cells of a memory, the states being determined in a time domain. If the n states do not form a code word of a k-from-n code, a plurality of states from the n states, which were determined within a reading window, are provided with a first valid assignment and fed to an error processing stage. If the error processing does not indicate an error, the n states are further processed with the first valid assignment, and if the error processing indicates an error, the plurality of states that were determined within the reading window are provided with a second valid assignment and the n states are further processed with the second valid assignment. Accordingly, a device, a system and a computer program product are also disclosed.Type: GrantFiled: September 19, 2019Date of Patent: October 26, 2021Assignee: Infineon Technologies AGInventors: Thomas Kern, Michael Goessel