Abstract: The determination of a code word is proposed, wherein (i) a bit group of n memory cells is read and n states are determined therefrom, the n states being determined in a time domain for each of at least two k-out-of-n codes, the at least two k-out-of-n codes having different k, (ii) the fact of whether a code word is present is determined for each of the at least two codes on the basis of the states, and (iii) when at least one code word is present, the code word of the k-out-of-n code having the largest k is used.

Abstract: A method for storing data bits in memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are stored in the memory cells. A method for reading data bits from memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are read from the memory cells based on the coded predefined functionality. Corresponding apparatuses and memories are also disclosed.

Abstract: A solution for correcting errors is proposed, wherein a bit group of n memory cells is read and n states are determined therefrom, wherein the n states are determined in a time domain for a k1-out-of-n code and for a k2-out-of-n code, where k1 is less than k2. Furthermore, for a read n-bit word, which is a non-code word instead of a code word of the k2-out-of-n code, the previously read n-bit code word of the k1-out-of-n code is used to determine possible erroneous bits in the read non-code word. Possible code words of the k2-out-of-n code are determined for the non-code word based on the possible erroneous bits, and error correction is carried out using an external error code based on the possible code words.

Abstract: Solutions are proposed related to error detection wherein (i) each byte of a second byte sequence is determined as a function of at least one byte of a first byte sequence, (ii) the second byte series is permissible if (a) it equals the corresponding byte of the first byte sequence or (b) an error being a member of a predetermined error set could cause the byte of the second byte sequence to become the byte of the first byte sequence, and otherwise (c) the byte of the second byte sequence is impermissible, and (iii) at least one error is detected if the second byte sequence is impermissible.

Abstract: The approaches proposed here relate to error processing by means of at least two error processing branches. Each of the error processing branches is configured (i) to process a data word, wherein the data words of the error processing branches differ in at least one bit, and (ii) to provide a processed data word to a decision unit. The decision unit is configured to select one of the processed data words or to perform a predetermined action if an uncorrectable error has been detected.

Abstract: Solutions are proposed related to error detection wherein (i) each byte of a second byte sequence is determined as a function of at least one byte of a first byte sequence, (ii) a byte of the second byte sequence is impermissible if it is not equal to an assigned byte of the first byte sequence and if no error of a predefined error set corrupts this byte to the assigned byte of the first byte sequence, and (iii) at least one error is detected if the second byte sequence is impermissible, the second byte sequence being impermissible if at least one byte of the second byte sequence is impermissible.

Abstract: An approach to correcting errors in a string of symbols is proposed, in which the string of symbols is transformed by a transformation ? into a first group of symbols and into a second group of symbols, and in which the group of symbols that has fewer erroneous symbols than the other group is corrected using a first error code.

Abstract: In accordance with an embodiment, a circuit arrangement includes a combinatorial circuit having a group of inputs and a group of outputs, where the combinatorial circuit is configured, during error-free operation of the combinatorial circuit, to map a codeword, present at the group of inputs, of a first error code to a codeword of a second error code at the group of outputs, and to map a non-codeword, present at the group of inputs, of the first error code to a non-codeword of the second error code; and a memory circuit configured to store an output of the combinatorial circuit at the group of outputs, and configured to correct at least 1-bit errors occurring during storage

Abstract: A solution is directed to determining an error in k data bits comprising the steps: determining the error, in particular the position of the error, based on M check bits and on n check bits; wherein the k data bits are arranged according to a structure; wherein the structure comprises the M check bits, wherein the M check bits are calculated based on the k data bits; wherein the structure comprises n groups, n being larger or equal to two, wherein each of the k data bits is associated with one of the n groups and wherein each of the n groups is associated with one of the n check bits.

Abstract: An approach corrects at least one byte error in a binary sequence, the binary sequence comprising multiple bytes and being a codeword of an error code if there is no error. The approach comprises: (i) determining at least one byte error position signal indicating whether or not a byte of the binary sequence is erroneous, (ii) determining at least one byte error correction value on the basis of which an erroneous byte position identified by using the byte error position signal is able to be corrected, (iii) wherein the at least one byte error correction value is determined by determining a first value, a second value and a third value for each of at least three byte positions according to a coefficient of the locator polynomial, and (iv) correcting the at least one byte error on the basis of the at least one byte error correction value.

Abstract: What is proposed is a solution for processing errors in a sequence of bits, wherein the sequence of bits, in the error-free case, forms a codeword of an error code, wherein the error code is based on an H-matrix or is able to be determined thereby, wherein an error syndrome is determined for the sequence of bits, wherein a link is determined between components of the error syndrome and parts of the H-matrix, and wherein two adjacent bits in the sequence of bits are corrected if the link adopts a predefined value.

Abstract: An approach for correcting at least one byte error in a binary sequence is proposed, the binary sequence comprising a plurality of bytes and being a code word of an error code in the error-free case. The approach comprises the steps of: (i) determining at least one byte error position signal which specifies whether or not a byte of the binary sequence is erroneous, (ii) determining at least one byte error correction value, based on which an erroneous byte position identified by means of the byte error position signal is correctable, the at least one byte error correction value being determined by virtue of a first value and a second value being determined for each of at least two byte positions based on a coefficient of the locator polynomial, and (iii) correcting the at least one byte error based on the at least one byte error correction value.

Abstract: The determination of a code word is proposed, wherein (i) a bit group of n memory cells is read and n states are determined therefrom, the n states being determined in a time domain for each of at least two k-out-of-n codes, the at least two k-out-of-n codes having different k, (ii) the fact of whether a code word is present is determined for each of the at least two codes on the basis of the states, and (iii) when at least one code word is present, the code word of the k-out-of-n code having the largest k is used.

Abstract: A solution is proposed for error processing, wherein n byte error positions of n byte errors are predefined (where n is a positive integer), wherein this involves determining whether there is a further byte error position on the basis of the n byte error positions and on the basis of n+1 error syndrome components of a first error code.

Abstract: Solutions are proposed related to error detection wherein (i) each byte of a second byte sequence is determined as a function of at least one byte of a first byte sequence, (ii) a byte of the second byte sequence is impermissible if it is not equal to an assigned byte of the first byte sequence and if no error of a predefined error set corrupts this byte to the assigned byte of the first byte sequence, and (iii) at least one error is detected if the second byte sequence is impermissible, the second byte sequence being impermissible if at least one byte of the second byte sequence is impermissible.

Abstract: An approach to correcting errors in a string of symbols is proposed, in which the string of symbols is transformed by a transformation ? into a first group of symbols and into a second group of symbols, and in which the group of symbols that has fewer erroneous symbols than the other group is corrected using a first error code.

Abstract: A method for storing data bits in memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are stored in the memory cells. A method for reading data bits from memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are read from the memory cells based on the coded predefined functionality. Corresponding apparatuses and memories are also disclosed.

Abstract: What is proposed is a solution for processing errors in a sequence of bits, wherein the sequence of bits, in the error-free case, forms a codeword of an error code, wherein the error code is based on an H-matrix or is able to be determined thereby, wherein an error syndrome is determined for the sequence of bits, wherein a link is determined between components of the error syndrome and parts of the H-matrix, and wherein two adjacent bits in the sequence of bits are corrected if the link adopts a predefined value.

Abstract: A method for storing data bits in memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are stored in the memory cells. A method for reading data bits from memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are read from the memory cells based on the coded predefined functionality. Corresponding apparatuses and memories are also disclosed.

Abstract: A method for determining a resultant data word when accessing memory cells includes reading a set of memory cells, and determining first and second data words therefrom. Each memory cell is assigned a component of the first and second data words. The first and second data words for the respective memory cell assume a first value if a first comparison with a first reference value and a second comparison with a second reference value show that the two reference values are greater and assume a second value if the first comparison with the first reference value and the second comparison with the second reference value show that the two reference values are smaller. The first and second data words assume at least one third value if neither condition is satisfied. The resultant data word is determined based on the first or second data words. A corresponding device is also proposed.