Patents by Inventor Michael Greer

Michael Greer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8364902
    Abstract: A microprocessor includes an instruction decoder for decoding a repeat prefetch indirect instruction that includes address operands used to calculate an address of a first entry in a prefetch table having a plurality of entries, each including a prefetch address. The repeat prefetch indirect instruction also includes a count specifying a number of cache lines to be prefetched. The memory address of each of the cache lines is specified by the prefetch address in one of the entries in the prefetch table. A count register, initially loaded with the count specified in the prefetch instruction, stores a remaining count of the cache lines to be prefetched. Control logic fetches the prefetch addresses of the cache lines from the table into the microprocessor and prefetches the cache lines from the system memory into a cache memory of the microprocessor using the count register and the prefetch addresses fetched from the table.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: January 29, 2013
    Assignee: VIA Technologies, Inc.
    Inventors: Rodney E. Hooker, John Michael Greer
  • Publication number: 20110238922
    Abstract: A data prefetcher in a microprocessor having a cache memory receives memory accesses each to an address within a memory block. The access addresses are non-monotonically increasing or decreasing as a function of time. As the accesses are received, the prefetcher maintains a largest address and a smallest address of the accesses and counts of changes to the largest and smallest addresses and maintains a history of recently accessed cache lines implicated by the access addresses within the memory block. The prefetcher also determines a predominant access direction based on the counts and determines a predominant access pattern based on the history. The prefetcher also prefetches into the cache memory, in the predominant access direction according to the predominant access pattern, cache lines of the memory block which the history indicates have not been recently accessed.
    Type: Application
    Filed: February 24, 2011
    Publication date: September 29, 2011
    Applicant: VIA Technologies, Inc.
    Inventors: Rodney E. Hooker, John Michael Greer
  • Publication number: 20110238923
    Abstract: A microprocessor includes a first-level cache memory, a second-level cache memory, and a data prefetcher that detects a predominant direction and pattern of recent memory accesses presented to the second-level cache memory and prefetches cache lines into the second-level cache memory based on the predominant direction and pattern. The data prefetcher also receives from the first-level cache memory an address of a memory access received by the first-level cache memory, wherein the address implicates a cache line. The data prefetcher also determines one or more cache lines indicated by the pattern beyond the implicated cache line in the predominant direction. The data prefetcher also causes the one or more cache lines to be prefetched into the first-level cache memory.
    Type: Application
    Filed: February 24, 2011
    Publication date: September 29, 2011
    Applicant: VIA Technologies, Inc.
    Inventors: Rodney E. Hooker, John Michael Greer
  • Publication number: 20110238920
    Abstract: A microprocessor includes a cache memory and a data prefetcher. The data prefetcher detects a pattern of memory accesses within a first memory block and prefetch into the cache memory cache lines from the first memory block based on the pattern. The data prefetcher also observes a new memory access request to a second memory block. The data prefetcher also determines that the first memory block is virtually adjacent to the second memory block and that the pattern, when continued from the first memory block to the second memory block, predicts an access to a cache line implicated by the new request within the second memory block. The data prefetcher also responsively prefetches into the cache memory cache lines from the second memory block based on the pattern.
    Type: Application
    Filed: February 24, 2011
    Publication date: September 29, 2011
    Applicant: VIA Technologies, Inc.
    Inventors: Rodney E. Hooker, John Michael Greer
  • Publication number: 20110035551
    Abstract: A microprocessor includes an instruction decoder for decoding a repeat prefetch indirect instruction that includes address operands used to calculate an address of a first entry in a prefetch table having a plurality of entries, each including a prefetch address. The repeat prefetch indirect instruction also includes a count specifying a number of cache lines to be prefetched. The memory address of each of the cache lines is specified by the prefetch address in one of the entries in the prefetch table. A count register, initially loaded with the count specified in the prefetch instruction, stores a remaining count of the cache lines to be prefetched. Control logic fetches the prefetch addresses of the cache lines from the table into the microprocessor and prefetches the cache lines from the system memory into a cache memory of the microprocessor using the count register and the prefetch addresses fetched from the table.
    Type: Application
    Filed: October 15, 2009
    Publication date: February 10, 2011
    Inventors: Rodney E. Hooker, John Michael Greer
  • Publication number: 20110010506
    Abstract: A data prefetcher includes a table of entries to maintain a history of load operations. Each entry stores a tag and a corresponding next stride. The tag comprises a concatenation of first and second strides. The next stride comprises the first stride. The first stride comprises a first cache line address subtracted from a second cache line address. The second stride comprises the second cache line address subtracted from a third cache line address. The first, second and third cache line addresses each comprise a memory address of a cache line implicated by respective first, second and third temporally preceding load operations. Control logic calculates a current stride by subtracting a previous cache line address from a new load cache line address, looks up in the table a concatenation of a previous stride and the current stride, and prefetches a cache line using the hitting table entry next stride.
    Type: Application
    Filed: October 5, 2009
    Publication date: January 13, 2011
    Applicant: VIA Technologies, Inc.
    Inventors: John Michael Greer, Rodney E. Hooker, Albert J. Loper, JR.
  • Publication number: 20100285847
    Abstract: A means of creation of joy and enjoyment plus self identification during the process of charging a cell phone.
    Type: Application
    Filed: May 9, 2009
    Publication date: November 11, 2010
    Inventors: Sarah Ann Greer, Keith Michael Greer
  • Patent number: 7255448
    Abstract: A display system includes a light source, a spatial light homogenizer, and imaging optics. The spatial light modulator has a plurality of modulator pixels. The display system also includes a pixelated plate illuminated by the light source. The pixelated plate has a plurality of individually defined pixels formed thereon. The spatial light modulator is in optical communication with the pixelated color management device by the imaging optics and each of the modulator pixels is associated with at least one of the individually defined pixels of the pixelated plate.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: August 14, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Michael Greer, David C. Collins, William J. Allen, Timothy F Myers
  • Publication number: 20060082560
    Abstract: A display system includes a light source, a spatial light homogenizer, and imaging optics. The spatial light modulator has a plurality of modulator pixels. The display system also includes a pixelated plate illuminated by the light source. The pixelated plate has a plurality of individually defined pixels formed thereon. The spatial light modulator is in optical communication with the pixelated color management device by the imaging optics and each of the modulator pixels is associated with at least one of the individually defined pixels of the pixelated plate.
    Type: Application
    Filed: October 20, 2004
    Publication date: April 20, 2006
    Inventors: Michael Greer, David Collins, William Allen, Timothy Myers
  • Patent number: 6980346
    Abstract: A method and apparatus includes receiving light at an intensity modulator. Subsequently, the light is received at an intensity-color modulator that includes at least one Fabry-Perot filter having a tunable optical property.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: December 27, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Michael Greer, Arthur R. Piehl
  • Publication number: 20050156715
    Abstract: An interface is provided for managing a plurality of tracked objects, each tracked object associated with a corresponding telemetry device. A request is received from a web browser for at least one action to be performed by the telemetry device. A message including information indicating the at least one action is transmitted, to the corresponding telemetry device. The web browser is configured to display at least one geographical map indication of at least one location of each tracked object.
    Type: Application
    Filed: January 16, 2004
    Publication date: July 21, 2005
    Inventors: Jie Zou, Vamsi Uppalapati, Michael Greer, Norman Goering
  • Publication number: 20040196910
    Abstract: The invention disclosed in this application uses a method of modulation named Integer Cycle Frequency Hopping (ICFH) wherein a carrier signal, comprised of a continuum of sine waves is generated on a single frequency. A data bit representing either a “1” or a “0”, depending upon the logic polarity chosen by the builder is imposed upon the carrier signal by modifying the carrier signal at precisely the zero crossing point or the zero degree angle. The method of imposing the data is to cause either a lengthening or shortening of the proceeding 360 degrees of phase angle, thus effectively either raising or lowering the frequency of the carrier signal for just the one, or a succession of cycles at hand. Upon completion of the 360-degree cycle(s), the carrier will return to the original frequency. The main carrier frequency is only modulated beginning at the zero degree phase angle and ending at the 360-degree phase angle.
    Type: Application
    Filed: January 27, 2004
    Publication date: October 7, 2004
    Applicant: xG Technology, LLC
    Inventors: Joseph Bobier, Michael Greer, Nadeem Khan
  • Patent number: 6782057
    Abstract: The present invention is addressed to a method of modulation wherein digital data streams are radio transmitted at a high level of efficiency and speed, and without a large continuous concomitant formation of side frequency phenomena. Thus, bandwidths assigned for this transmissional task are quite narrow, with data transmission speeds at the singular frequency of the RF carrier itself. This invention can send high-speed data in RF channels that are very narrow and that would ordinarily be considered useful only for very low speed data or analog voice. The purpose of this invention is to provide a means by which a radio frequency carrier, expressed, as a square wave can be amplitude modulated with maximum efficiency and speed with minimum phase delay and distortion. RF filtering is used to reduce the modulated square wave to its base band sine wave component after modulation. This circuit may be used to modulate the carrier (clock) at any frequency up to and beyond the carrier frequency itself.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: August 24, 2004
    Assignee: XG Technology, LLC
    Inventors: Michael Greer, Nadeem Khan
  • Publication number: 20030112892
    Abstract: The present invention is addressed to a method of modulation wherein digital data streams are radio transmitted at a high level of efficiency and speed, and without a large continuous concomitant formation of side frequency phenomena. Thus, bandwidths assigned for this transmissional task are quite narrow, with data transmission speeds at the singular frequency of the RF carrier itself. This invention can send high-speed data in RF channels that are very narrow and that would ordinarily be considered useful only for very low speed data or analog voice. The purpose of this invention is to provide a means by which a radio frequency carrier, expressed, as a square wave can be amplitude modulated with maximum efficiency and speed with minimum phase delay and distortion. RF filtering is used to reduce the modulated square wave to its base band sine wave component after modulation. This circuit may be used to modulate the carrier (clock) at any frequency up to and beyond the carrier frequency itself.
    Type: Application
    Filed: December 17, 2002
    Publication date: June 19, 2003
    Applicant: Island Labs, LLC
    Inventors: Michael Greer, Nadeem Khan
  • Patent number: 6386550
    Abstract: A subterranean coupler for slidably receiving a pipe therethrough and for coupling the pipe to a subterranean vessel. The coupler is mountable to a reinforcing grid prior to the coupler and reinforcing grid being cast in a concrete wall of the subterranean vessel. The coupler includes a longitudinally-extending axis and a cylindrical wall defined about the axis, the wall having an inner surface, an outer surface, and first and second ends. The coupler further includes a plurality of radially-extending, circumferentially-spaced engagement members integrally-formed with the outer surface. The engagement members are engageable with grid members of the reinforcing grid to mount the cylindrical wall to the reinforcing grid prior to casting.
    Type: Grant
    Filed: February 2, 2000
    Date of Patent: May 14, 2002
    Assignee: Stepcon Industries Inc.
    Inventors: John Mokrzycki, Michael Greer