Abstract: Transistor structures for a transistor may include a first source-drain region, a second source-drain region, and a channel region between the first and second source-drain regions overlapped by a gate structure. Transistor structures may be formed in a well of a first doping type. Isolation structures having the first doping type may be formed within the well. A lightly doped implant region of a second doping type for each of the source-drain regions may be formed within the well and separated from the isolation structures. A heavily doped surface implant region of the first doping type may extend across the surface of the well and cover the lightly doped implant region of each source-drain region. The surface implant region may be formed by patterning or by a blanket implantation process across the transistor structures.

Abstract: An image sensor may include an array of image pixels. The array of image pixel may be coupled to control circuitry and readout circuitry. One or more image pixels in the array may each include a coupled-gates structure coupling a photodiode at one input terminal to a capacitor at a first output terminal and to a floating diffusion region at a second output terminal. The coupled-gates structure may include a first transistor that sets a potential barrier defining overflow portions of the photodiode-generated charge. Second and third transistors in the coupled-gates structure may be modulated to transfer the overflow charge to the capacitor and to the floating diffusion region at suitable times. The second and third transistors may form a conductive path between the capacitor and the floating diffusion region for a low conversion gain mode of operation.

Abstract: A pixel array within an integrated-circuit image sensor includes four sets of photodetection elements disposed in respective pixel-array regions having a shared corner, four readout circuits each coupled to a respective one of the four sets of photodetection elements, a reset node, a reset transistor, and binning transistors. Each of the four readout circuits has a floating diffusion node, a first transfer gate coupled between the floating diffusion node and a constituent photodetection element of the respective one of the four sets of photodetection elements, and an amplifier transistor having a gate terminal coupled to the floating diffusion node. The reset transistor is coupled between the reset node and a reset-voltage supply, and each one of the binning transistors is coupled between the reset node and the floating diffusion node of a respective one of the readout circuits.

Abstract: Photodetection elements within an integrated-circuit pixel array are dynamically configurable to any of at least three uniform-aspect-ratio, size-scaled pixel footprints through read-out-time control of in-pixel transfer gates associated with respective photodetection elements and binning transistors coupled between the transfer gates for respective clusters of the photodetection elements and a shared reset node.

Abstract: Transistor structures for a transistor may include a first source-drain region, a second source-drain region, and a channel region between the first and second source-drain regions overlapped by a gate structure. Transistor structures may be formed in a well of a first doping type. Isolation structures having the first doping type may be formed within the well. A lightly doped implant region of a second doping type for each of the source-drain regions may be formed within the well and separated from the isolation structures. A heavily doped surface implant region of the first doping type may extend across the surface of the well and cover the lightly doped implant region of each source-drain region. The surface implant region may be formed by patterning or by a blanket implantation process across the transistor structures.

Abstract: A pixel array within an integrated-circuit image sensor includes four sets of photodetection elements disposed in respective pixel-array regions having a shared corner, four readout circuits each coupled to a respective one of the four sets of photodetection elements, a reset node, a reset transistor, and binning transistors. Each of the four readout circuits has a floating diffusion node, a first transfer gate coupled between the floating diffusion node and a constituent photodetection element of the respective one of the four sets of photodetection elements, and an amplifier transistor having a gate terminal coupled to the floating diffusion node. The reset transistor is coupled between the reset node and a reset-voltage supply, and each one of the binning transistors is coupled between the reset node and the floating diffusion node of a respective one of the readout circuits.

Abstract: An image sensor includes an array of CMOS pixels and a plurality of micro-lens arrays. Each micro-lens array of the plurality of micro-lens arrays includes a plurality of horizontally adjacent micro-lenses. Each micro-lens array of the plurality of micro-lens arrays is situated above a respective CMOS pixel in the array of CMOS pixels.

Abstract: An image sensor may include an array of image pixels. The array of image pixel may be coupled to control circuitry and readout circuitry. One or more image pixels in the array may each include a coupled-gates structure coupling a photodiode at one input terminal to a capacitor at a first output terminal and to a floating diffusion region at a second output terminal. The coupled-gates structure may include a first transistor that sets a potential barrier defining overflow portions of the photodiode-generated charge. Second and third transistors in the coupled-gates structure may be modulated to transfer the overflow charge to the capacitor and to the floating diffusion region at suitable times. The second and third transistors may form a conductive path between the capacitor and the floating diffusion region for a low conversion gain mode of operation.

Abstract: An image sensor may include an array of image pixels. The array of image pixel may be coupled to control circuitry and readout circuitry. One or more image pixels in the array may each include a coupled-gates structure coupling a photodiode at one input terminal to a capacitor at a first output terminal and to a floating diffusion region at a second output terminal. The coupled-gates structure may include a first transistor that sets a potential barrier defining overflow portions of the photodiode-generated charge. Second and third transistors in the coupled-gates structure may be modulated to transfer the overflow charge to the capacitor and to the floating diffusion region at suitable times. The second and third transistors may form a conductive path between the capacitor and the floating diffusion region for a low conversion gain mode of operation.

Abstract: Photodetection elements within an integrated-circuit pixel array are dynamically configurable to any of at least three uniform-aspect-ratio, size-scaled pixel footprints through read-out-time control of in-pixel transfer gates associated with respective photodetection elements and binning transistors coupled between the transfer gates for respective clusters of the photodetection elements and a shared reset node.

Abstract: Signals representative of total photocharge integrated within respective image-sensor pixels are read out of the pixels after a first exposure interval that constitutes a first fraction of a frame interval. Signals in excess of a threshold level are read out of the pixels after an ensuing second exposure interval that constitutes a second fraction of the frame interval, leaving residual photocharge within the pixels. After a third exposure interval that constitutes a third fraction of the frame interval, signals representative of a combination of at least the residual photocharge and photocharge integrated within the pixels during the third exposure interval are read out of the pixels.

Abstract: An image sensor includes an array of CMOS pixels and a plurality of micro-lens arrays. Each micro-lens array of the plurality of micro-lens arrays includes a plurality of horizontally adjacent micro-lenses. Each micro-lens array of the plurality of micro-lens arrays is situated above a respective CMOS pixel in the array of CMOS pixels.

Abstract: An imaging system may include an image sensor having an image sensor. The image sensor may include an image sensor pixel array coupled to row control circuitry and column readout circuitry. The image sensor pixel array may include a plurality of image sensor pixels. Each image sensor pixel may include a photosensitive element configured to generate charge in response to incident light, a first charge storage structure configured to accumulate an overflow portion of the generated charge for a low gain signal and a second charge storage structure configured to store a remaining portion of the generated charge for a high gain signal. Each image sensor pixel may also include a dedicated overflow charge storage structure interposed between the first charge storage structure and a floating diffusion region.

Abstract: Photodetection elements within an integrated-circuit pixel array are dynamically configurable to any of at least three uniform-aspect-ratio, size-scaled pixel footprints through read-out-time control of in-pixel transfer gates associated with respective photodetection elements and binning transistors coupled between the transfer gates for respective clusters of the photodetection elements and a shared reset node.

Abstract: Photodetection elements within an integrated-circuit pixel array are dynamically configurable to any of at least three uniform-aspect-ratio, size-scaled pixel footprints through read-out-time control of in-pixel transfer gates associated with respective photodetection elements and binning transistors coupled between the transfer gates for respective clusters of the photodetection elements and a shared reset node.

Abstract: A control pulse is generated a first control signal line coupled to a transfer gate of a pixel to enable photocharge accumulated within a photosensitive element of the pixel to be transferred to a floating diffusion node, the first control signal line having a capacitive coupling to the floating diffusion node. A feedthrough compensation pulse is generated on a second signal line of the pixel array that also has a capacitive coupling to the floating diffusion node. The feedthrough compensation pulse is generated with a pulse polarity opposite the pulse polarity of the control pulse and is timed to coincide with the control pulse such that capacitive feedthrough of the control pulse to the floating diffusion node is reduced.

Abstract: An imaging system may include an image sensor having an image sensor. The image sensor may include an image sensor pixel array coupled to row control circuitry and column readout circuitry. The image sensor pixel array may include a plurality of image sensor pixels. Each image sensor pixel may include a photosensitive element configured to generate charge in response to incident light, a first charge storage structure configured to accumulate an overflow portion of the generated charge for a low gain signal and a second charge storage structure configured to store a remaining portion of the generated charge for a high gain signal. Each image sensor pixel may also include a dedicated overflow charge storage structure interposed between the first charge storage structure and a floating diffusion region.

Abstract: An image sensor includes an array of CMOS pixels and a plurality of micro-lens arrays. Each micro-lens array of the plurality of micro-lens arrays includes a plurality of horizontally adjacent micro-lenses. Each micro-lens array of the plurality of micro-lens arrays is situated above a respective CMOS pixel in the array of CMOS pixels.

Abstract: Signals representative of total photocharge integrated within respective image-sensor pixels are read out of the pixels after a first exposure interval that constitutes a first fraction of a frame interval. Signals in excess of a threshold level are read out of the pixels after an ensuing second exposure interval that constitutes a second fraction of the frame interval, leaving residual photocharge within the pixels. After a third exposure interval that constitutes a third fraction of the frame interval, signals representative of a combination of at least the residual photocharge and photocharge integrated within the pixels during the third exposure interval are read out of the pixels.

Abstract: A pixel array within an integrated-circuit image sensor is exposed to light representative of a scene during a first frame interval and then oversampled a first number of times within the first frame interval to generate a corresponding first number of frames of image data from which a first output image may be constructed. One or more of the first number of frames of image data are evaluated to determine whether a range of luminances in the scene warrants adjustment of an oversampling factor from the first number to a second number, if so, the oversampling factor is adjusted such that the pixel array is oversampled the second number of times within a second frame interval to generate a corresponding second number of frames of image data from which a second output image may be constructed.