Abstract: Integrated circuits with charge pumps are frequently used for supplying integrated circuits, in particular memory circuits, with energy. When the input voltages are low, at about 2V or less, the required operating voltage may be less than the required 2.5V or 3.3V. In that case it is no longer ensured that the integrated circuit will operate reliably. A two-stage charge pump is thus provided, in which the second stage is connected with its capacitor in parallel with the first stage. The parallel circuit allows the ratio of the two capacitances to be determined largely freely as a function of predetermined parameters, such as the current, the voltage and the required area. Furthermore, this also has the advantage over a series circuit that, when the two capacitances are connected in parallel, they are added linearly, so that the capacitance size can be defined largely independently and freely.

Abstract: Circuit arrangement for determining the load current through an inductive load (L) connected to a supply voltage (Vbat) in a clocked manner includes a current measuring impedance (30) which can be connected in series with the inductive load (L), a first and second connecting terminal (31, 32), a measuring amplifier (20) having a first and second input (21, 22) and an output (23), and a level shifter arrangement (40) having first and second inputs (41, 42) and first and second outputs (43, 44) The arrangement is designed to map a potential present at the first input terminal (41) onto a potential shifted by a predetermined potential value at the first output terminal (43) and to map a potential present at the second input terminal (42) onto a potential shifted by a predetermined potential value at the second output terminal (44).

Abstract: Integrated circuits with charge pumps are frequently used for supplying integrated circuits, in particular memory circuits, with energy. When the input voltages are low, at about 2V or less, the required operating voltage may be less than the required 2.5V or 3.3V. In that case it is no longer ensured that the integrated circuit will operate reliably. A two-stage charge pump is thus provided, in which the second stage is connected with its capacitor in parallel with the first stage. The parallel circuit allows the ratio of the two capacitances to be determined largely freely as a function of predetermined parameters, such as the current, the voltage and the required area. Furthermore, this also has the advantage over a series circuit that, when the two capacitances are connected in parallel, they are added linearly, so that the capacitance size can be defined largely independently and freely.

Abstract: An integrated semiconductor apparatus includes at least one fuse box device that includes fuses for storing trimming data, a fuse box trimming output, and a timer emitting a clock signal. The apparatus also includes a parallel/serial converter that is connected to the fuses and to the timer. The parallel/serial converter is configured to read, in parallel, the trimming data from the fuses and to emit, in serial, the trimming data from the fuse block trimming output based on the clock signal. The apparatus also includes generators. Each generator generates a generator signal and includes a trimming unit that has a trimming signal input. The trimming unit is configured to trim the generator signal of the generator based on the trimming data received. The generator also includes a trimming signal output and memory flip-flops that connect the trimming input signal to the trimming output signal.

Abstract: An increased internal operating voltage for an integrated circuit can be generated with two two-stage charge pumps, ensuring reliable operation even in the event of an external voltage supply Vext=1.8 V or less. The two charge pumps cooperate with a common first stage in a cyclic sequence. A temporally offset organization of the cycles of the two charge pumps enables operation in a manner that is free from disturbances. Moreover, the large chip area required for capacitors can advantageously be considerably reduced.

Abstract: The invention relates to a signal generating device (10) for a charge pump for an integrated circuit, comprising: N signal outputs D1, . . . , DN and a signal setting input (12) for setting a frequency f, in which case the signal generating device (10) is designed in such a way that a periodic signal Sx(t) can be output via the signal output Dx, all the signals S1(t), . . . , SN(t) have the same settable frequency f, in which case the following holds true for the signal Sx(t), where 2≦x≦N, Sx(t)=S1(t−(x−1)·&Dgr;Tx−kx/(2f)), in which case &Dgr;Tx is the delay duration of the signal Sx(t) with respect to Sx−1(t), and kx&egr;{0; 1}, the delay duration &Dgr;tx is dependent on the frequency f. Furthermore, the invention relates to an integrated circuit.

Abstract: The invention relates to a device (10) for outputting a refresh signal for a memory cell of a semiconductor memory device, the device (10) comprising: a receiving device for receiving a variable periodic refresh input signal (14); a comparison device (22) for comparing the period duration of the refresh input signal (14) with at least one predeterminable value; an output device (22) for outputting a refresh output signal (24) in a manner dependent on the result of the comparison in the comparison device (22); the output device (22) being designed in such a way that if the period duration of the refresh input signal (14) lies above a predeterminable maximum value, a refresh output signal (24) with the predeterminable maximum period duration (T_max) can be output and/or if the period duration of the refresh input signal (14) lies below a predeterminable minimum value, a refresh output signal (24) with a predeterminable minimum period duration (T_min) can be output, and otherwise a refresh output signal (2

Abstract: A method and circuit for refreshing dynamic memory cells arranged along word lines and bit lines are provided, the memory cells being refreshed in a manner dependent on a refresh signal with a refresh frequency by the activation of the word line in order to write the information back to the memory cells arranged on the relevant word line, in which case the refresh frequency is set in a manner dependent on the charge loss of first dummy memory cells during a refresh period of the refresh signal on a first dummy word line and/or in a manner dependent on the charge loss of second dummy memory cells during the refresh period of the refresh signal on a second dummy word line.

Abstract: A circuit has a control signal input, a control signal output, a delay element for generating a delay duration, and a control logic circuit. The latter controls the delay element and switches a change in the state at the control signal input to the control signal output in a manner delayed by the delay element, if a minimum time interval between state changes at the control signal input is undershot. The circuit is employed in DRAMs for controlling the active times of the voltage generators present in DRAMs.

Abstract: The invention features an output driver device for an integrated circuit that includes an output device having an output terminal for an output signal to be output from the output driver device, an input terminal for an input signal to be input into the output driver device, and a control device that is signal-connected to the output device and the input terminal and is designed to transform the input signal into two mutually different control signals and to output the control signals via control signal outputs to the output device, where the output device configured to generate the output signal in a manner dependent on the control signals.

Abstract: The invention relates to a signal generating device (10) for a charge pump for an integrated circuit, comprising:

Abstract: The invention relates to a device (10) for outputting a refresh signal for a memory cell of a semiconductor memory device, the device (10) comprising:

Abstract: An increased internal operating voltage for an integrated circuit can be generated with two two-stage charge pumps, ensuring reliable operation even in the event of an external voltage supply Vext=1.8 V or less. The two charge pumps cooperate with a common first stage in a cyclic sequence. A temporally offset organization of the cycles of the two charge pumps enables operation in a manner that is free from disturbances. Moreover, the large chip area required for capacitors can advantageously be considerably reduced.

Abstract: A circuit has a control signal input, a control signal output, a delay element for generating a delay duration, and a control logic circuit. The latter controls the delay element and switches a change in the state at the control signal input to the control signal output in a manner delayed by the delay element, if a minimum time interval between state changes at the control signal input is undershot. The circuit is employed in DRAMs for controlling the active times of the voltage generators present in DRAMs.

Abstract: The invention features an output driver device for an integrated circuit that includes an output device having an output terminal for an output signal to be output from the output driver device, an input terminal for an input signal to be input into the output driver device, and a control device that is signal-connected to the output device and the input terminal and is designed to transform the input signal into two mutually different control signals and to output the control signals via control signal outputs to the output device, where the output device configured to generate the output signal in a manner dependent on the control signals.

Abstract: The invention concerns a method and devices for far field microscopy and flow fluorometry for geometric distance measurements between object structures, i.e. measurement structures, marked with fluorochromes, whereby the distances can be smaller than the half-intensity width of the principle maximum of the point spread function. In this method, the measurement structures are marked with fluorescent dyes with different or identical spectral signatures, according to their distances. Calibration targets with defined dimensions and arrays are marked with the same fluorescent dyes. Calibration targets and measurement structures are prepared separately or together on an object support and investigated microscopically or flow fluorometrically.