Patents by Inventor Michael Hemsley Wood
Michael Hemsley Wood has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240104282Abstract: A method, system, and computer program product for bit flip aware latch placement in integrated circuit generation are provided. The method identifies a chip design for an integrated circuit. A set of chip design constraints, associated with the chip design, is identified. A set of checking groups, associated with a plurality of latches to be placed in the chip design, is determined. Based on the set of chip design constraints and the set of checking groups, a placement scheme for the plurality of latches is selected. The method places the plurality of latches within the chip design based on the placement scheme and the set of checking groups.Type: ApplicationFiled: September 22, 2022Publication date: March 28, 2024Inventors: Benjamin Neil Trombley, Chung-Lung K. Shum, Paul G. Villarrubia, K. Paul Muller, Michael Hemsley Wood, Daniel Arthur Gay, Hua Xiang, Karl Evan Smock Anderson, Erica Stuecheli, Michael Alexander Bowen, Randall J. Darden
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Patent number: 11916384Abstract: Embodiments for power generation include defining a power tile within a power distribution network having a grid of power rails, the power tile having logic gates, and applying an initial power grid pattern from a plurality of power grid patterns for the power tile such that initial power grid pattern relates to timing characteristics of the logic gates of the power tile. The power grid patterns each have a different number of connectors connecting one power rail to another power rail in the grid of power rails. A subsequent power grid pattern is selected from the power grid patterns for the power tile such that the subsequent power grid pattern meets a threshold condition for the timing characteristics of the logic gates of the power tile. The timing characteristics for the logic gates are determined based on a voltage drop associated with the subsequent power grid pattern.Type: GrantFiled: September 20, 2021Date of Patent: February 27, 2024Assignee: International Business Machines CorporationInventors: David Wolpert, Basanth Jagannathan, Michael Hemsley Wood, Leon Sigal, James Leland, Alexander Joel Suess, Benjamin Neil Trombley, Paul G. Villarrubia
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Patent number: 11906570Abstract: A method is provided to increase processor frequency in an integrated circuit (IC). The method includes identifying a gate included in the IC, the gate having a gate threshold voltage and performing a plasma process to form an antenna signal path in signal communication with the gate. The method further comprises adjusting the plasma process or circuit design to increase plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage.Type: GrantFiled: April 6, 2023Date of Patent: February 20, 2024Assignee: International Business Machines CorporationInventors: Christopher Gonzalez, David Wolpert, Michael Hemsley Wood
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Patent number: 11797740Abstract: A system is provided to perform slack apportionment for an integrated circuit. The system includes a time calculation module and a slack apportion module. The time calculation module determines an arrival time corresponding to a target pin in signal communication with a signal path. The slack apportion module determines a total slack associated with the signal path and determines a slack threshold value that is equal to a portion of the total slack. The time calculation module further determines an apportioned arrival time associated with the signal path based on the arrival time and a delay offset value. The slack apportion module further determines a residual slack apportionment value based on a residual slack and the number of macros associated with the signal path. Accordingly, the time calculation module determines a modified apportioned arrival time based on the residual slack apportionment value and the apportioned arrival time.Type: GrantFiled: February 15, 2022Date of Patent: October 24, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jesse Peter Surprise, Eduard Herkel, Ofer Geva, Michael Hemsley Wood, Chris Aaron Cavitt, Tsz-Mei Ko
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Publication number: 20230306176Abstract: Method and apparatus for generating an updated power delivery network. Generating the power delivery network includes determining power characteristics for a power delivery network of a circuit design based on logic cells of the circuit design. The power delivery network includes power wires and power staples connecting pairs of the power wires to each other. Further a first one or more of the power staples is remove from the power delivery network based on the power characteristics. Signal wires for the logic cells are routed after removing the first one or more of the power staples. Routing the signal wires includes routing a first signal wire of the signal wires in a routing track corresponding to the first one or more of the power staples.Type: ApplicationFiled: March 23, 2022Publication date: September 28, 2023Inventors: David WOLPERT, Matthew T. GUZOWSKI, Michael Hemsley WOOD, Leon SIGAL
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Patent number: 11754615Abstract: A method is provided to increase processor frequency in an integrated circuit (IC). The method includes identifying a gate included in the IC, the gate having a gate threshold voltage and performing a plasma process to form an antenna signal path in signal communication with the gate. The method further comprises adjusting the plasma process or circuit design to increase plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage.Type: GrantFiled: September 21, 2021Date of Patent: September 12, 2023Assignee: International Business Machines CorporationInventors: Christopher Gonzalez, David Wolpert, Michael Hemsley Wood
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Publication number: 20230281365Abstract: Aspects of the invention include determining a netlist for an integrated circuit design, wherein the netlist includes a design for placement of a plurality of latches, determining a set of timing paths, wherein each timing path includes a capture latch and at least one launch latch connected to a same local clock buffer controller through a local clock buffer OR circuit, calculating a slack value for each timing path, determining one or more candidate timing paths from the set of timing paths, wherein the one or more candidate timing paths have a slack value below a threshold slack value, calculating a score for each candidate timing path based on a count of a number of launch-capture latch pairs, adjusting an interconnect for a first candidate timing path based on the first candidate timing path having a highest score, and generating an updated netlist based on the adjusting the interconnect.Type: ApplicationFiled: March 2, 2022Publication date: September 7, 2023Inventors: Michael Kazda, Sean Michael Carey, Frank J. Musante, Michael Hemsley Wood
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Publication number: 20230259679Abstract: A system is provided to perform slack apportionment for an integrated circuit. The system includes a time calculation module and a slack apportion module. The time calculation module determines an arrival time corresponding to a target pin in signal communication with a signal path. The slack apportion module determines a total slack associated with the signal path and determines a slack threshold value that is equal to a portion of the total slack. The time calculation module further determines an apportioned arrival time associated with the signal path based on the arrival time and a delay offset value. The slack apportion module further determines a residual slack apportionment value based on a residual slack and the number of macros associated with the signal path. Accordingly, the time calculation module determines a modified apportioned arrival time based on the residual slack apportionment value and the apportioned arrival time.Type: ApplicationFiled: February 15, 2022Publication date: August 17, 2023Inventors: Jesse Peter Surprise, Eduard Herkel, OFER GEVA, Michael Hemsley Wood, Chris Aaron Cavitt, TSZ-MEI KO
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Publication number: 20230251299Abstract: A method is provided to increase processor frequency in an integrated circuit (IC). The method includes identifying a gate included in the IC, the gate having a gate threshold voltage and performing a plasma process to form an antenna signal path in signal communication with the gate. The method further comprises adjusting the plasma process or circuit design to increase plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage.Type: ApplicationFiled: April 6, 2023Publication date: August 10, 2023Inventors: Christopher Gonzalez, David Wolpert, Michael Hemsley Wood
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Publication number: 20230090855Abstract: Embodiments for power generation include defining a power tile within a power distribution network having a grid of power rails, the power tile having logic gates, and applying an initial power grid pattern from a plurality of power grid patterns for the power tile such that initial power grid pattern relates to timing characteristics of the logic gates of the power tile. The power grid patterns each have a different number of connectors connecting one power rail to another power rail in the grid of power rails. A subsequent power grid pattern is selected from the power grid patterns for the power tile such that the subsequent power grid pattern meets a threshold condition for the timing characteristics of the logic gates of the power tile. The timing characteristics for the logic gates are determined based on a voltage drop associated with the subsequent power grid pattern.Type: ApplicationFiled: September 20, 2021Publication date: March 23, 2023Inventors: David Wolpert, Basanth Jagannathan, Michael Hemsley Wood, Leon Sigal, James Leland, Alexander Joel Suess, Benjamin Neil Trombley, Paul G. Villarrubia
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Publication number: 20230086010Abstract: A method is provided to increase processor frequency in an integrated circuit (IC). The method includes identifying a gate included in the IC, the gate having a gate threshold voltage and performing a plasma process to form an antenna signal path in signal communication with the gate. The method further comprises adjusting the plasma process or circuit design to increase plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage.Type: ApplicationFiled: September 21, 2021Publication date: March 23, 2023Inventors: Christopher Gonzalez, David Wolpert, Michael Hemsley Wood
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Publication number: 20230070516Abstract: A first plurality of hardware description language (HDL) files describe a hierarchical integrated circuit design utilizing a simplified HDL syntax that omits specification of logical clock connections for at least some entities in the hierarchical integrated circuit design. The hierarchical integrated circuit design as described by the first plurality of HDL files is processed to automatically add logical clock connections for entities in the hierarchical integrated circuit design for which specification of logical clock connections are omitted in the first plurality of HDL files. Based on the processing, a second plurality of HDL files defining the hierarchical integrated circuit design is generated.Type: ApplicationFiled: September 7, 2021Publication date: March 9, 2023Inventors: Ali S. El-Zein, Viresh Paruthi, Alvan Wing Ng, Benedikt Geukes, Klaus-Dieter Schubert, Robert Alan Cargnoni, Michael Hemsley Wood, Stephen Gerard Shuma, Wolfgang Roesner, Chung-Lung K. Shum, Edward Armayor McQuade, Derek E. Williams
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Publication number: 20230072735Abstract: A processor receives an expression of design refinement intent with regard to an entity forming a part of a modular circuit design. The entity is defined by a hardware description language (HDL) file, and the expression of design refinement intent identifies an intent region within an implementation of the entity and specifies replacement logic for the region. Based on the expression of design refinement intent, the processor automatically modifies the HDL file by replacing logic within the intent region with the replacement logic. The processor then performs logical synthesis to generate a gate list representation of the modular circuit design as modified.Type: ApplicationFiled: September 7, 2021Publication date: March 9, 2023Inventors: Ali S. El-Zein, Wolfgang Roesner, Stephen Gerard Shuma, Robert Lowell Kanzelman, Michael Hemsley Wood, Chung-Lung K. Shum, Gabor Bobok, Robert James Shadowen, Viresh Paruthi, Derek E. Williams
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Patent number: 11093675Abstract: A statistical single-input switching (SIS) timing value is obtained for a first input of a device. A side input with an arc to a common output of a circuit is selected and a statistical skew for the first input and the selected side input of the circuit is obtained. An expected-value for a statistical scale factor distribution is convolved and computed based on the statistical skew. The statistical single-input switching (SIS) timing value is scaled with a final effective statistical scale factor based on the expected-value; optionally, sensitivities of the statistical timing value to variational parameters are chain-ruled with the sensitivities of the statistical skew to variational parameters; and a statistical timing analysis of a given VLSI design is generated based on the scaled (and optionally, chain-ruled) statistical single-input switching (SIS) timing value to create the improved VLSI circuit design.Type: GrantFiled: March 18, 2020Date of Patent: August 17, 2021Assignee: International Business Machines CorporationInventors: Debjit Sinha, Vasant Rao, Michael Hemsley Wood
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Patent number: 11074379Abstract: For each of a plurality of source-sink pairs, a corresponding interconnect layer is selected having a reach length which permits propagation of a required signal within a required sink cycle delay. For a first clock cycle, a movable region for a first latch is located as a first plurality of overlapped regions one reach length from a source and the required sink cycle delay number of reach lengths from each one of the sinks; and the first plurality of overlapped regions is represented as nodes on a first cycle level of a topology search graph. Analogous actions are carried out for a second clock cycle of the required sink cycle delay. A latch tree is created based on the topology search graph, wherein a required number of latches is minimized, and at each of the cycle levels, all sinks of source nodes selected at a previous level are covered.Type: GrantFiled: March 30, 2019Date of Patent: July 27, 2021Assignee: International Business Machines CorporationInventors: Lakshmi N. Reddy, Gustavo Enrique Tellez, Paul G. Villarrubia, Christopher Joseph Berry, Michael Hemsley Wood, Robert A. Philhower, Gi-Joon Nam, Jinwook Jung
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Patent number: 10831954Abstract: Efficiency of electronic design automation is increased by accessing a data structure characterizing a hierarchical integrated circuit design including sub-blocks each with a plurality of ports. For each given one of the ports of each of the sub-blocks, obtain a wire specification for a corresponding net connected to the given one of the ports in the design, and based on the wire specification, consult a technology-specific lookup table to determine at least one of a corresponding default driving cell and default electrical model for an external wire coupling one of the default driving cell and an actual driving cell to the given one of the ports. Optimize each of the sub-blocks out-of-context based on the at least one of default driving cells and default electrical models; verify in-context closure for the optimized sub-blocks; and, responsive to the in-context closure, update the data structure to reflect the optimized sub-blocks.Type: GrantFiled: October 29, 2019Date of Patent: November 10, 2020Assignee: International Business Machines CorporationInventors: Debjit Sinha, Ravi Chander Ledalla, Chaobo Li, Adil Bhanji, Gregory Schaeffer, Michael Hemsley Wood
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Publication number: 20200311221Abstract: For each of a plurality of source-sink pairs, a corresponding interconnect layer is selected having a reach length which permits propagation of a required signal within a required sink cycle delay. For a first clock cycle, a movable region for a first latch is located as a first plurality of overlapped regions one reach length from a source and the required sink cycle delay number of reach lengths from each one of the sinks; and the first plurality of overlapped regions is represented as nodes on a first cycle level of a topology search graph. Analogous actions are carried out for a second clock cycle of the required sink cycle delay. A latch tree is created based on the topology search graph, wherein a required number of latches is minimized, and at each of the cycle levels, all sinks of source nodes selected at a previous level are covered.Type: ApplicationFiled: March 30, 2019Publication date: October 1, 2020Inventors: Lakshmi N. Reddy, Gustavo Enrique Tellez, Paul G. Villarrubia, Christopher Joseph Berry, Michael Hemsley Wood, Robert A. Philhower, Gi-Joon Nam, Jinwook Jung
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Patent number: 10254784Abstract: Coupled noise from at least one out-of-context aggressor net of an integrated circuit design is computed for an out-of-context victim net. The nets are out-of-context with respect to a hierarchical noise analysis of the integrated circuit design. At least one of the nets is a continuation of a path which extends to at least one in-context portion of the integrated circuit design. An aggressor signal timing window is derived for the at least one out-of-context aggressor net; a victim signal timing window is derived for the out-of-context victim net; and a timing window and noise analysis is completed with the aggressor signal timing window and the victim signal timing window. The aggressor window is derived as a function of required arrival time of the at least one out-of-context aggressor net and/or the victim window is derived as a function of required arrival time of the out-of-context victim net.Type: GrantFiled: July 24, 2018Date of Patent: April 9, 2019Assignee: International Business Machines CorporationInventors: Jason David Morsey, Steven Eugene Washburn, Patrick M. Williams, Michael Hemsley Wood
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Patent number: 8001411Abstract: A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times itscommencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes.Type: GrantFiled: September 24, 2007Date of Patent: August 16, 2011Assignee: International Business Machines CorporationInventors: Sean Michael Carey, William Vincent Huott, Christian Jacobi, Guenter Mayer, Timothy Gerard McNamara, Chung-Lung Kevin Shum, Hans-Werner Tast, Michael Hemsley Wood
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Patent number: 7971162Abstract: A method to assess spare latch placement in a macro, the method comprises steps of: determining a location for each spare latch in the macro; examining local clock buffers associated with the macro to locate any local clock buffers without a spare latch directly attached to clock nets driven by said local clock buffer; measuring a distance between each of the local clock buffers without spare latches and a closest spare latch; running statistics for the local clock buffers from the measuring step; and locating macros with inadequate spare latch placement using the statistics.Type: GrantFiled: February 18, 2008Date of Patent: June 28, 2011Assignee: International Business Machines CorporationInventor: Michael Hemsley Wood