Abstract: A method for determining gate array distribution includes steps or acts of: randomly placing a plurality of test boxes in a logic circuit layout; counting the number of fill cells in each of the plurality of test boxes; recording the count; grouping the plurality of test boxes into two groups: a first group with local clock buffers and a second group without local clock buffers; determining the fill cell percentage of each of the plurality of test boxes; and flagging the test boxes with a poor distribution of gate array cells.

Abstract: A method to assess spare latch placement in a macro, the method comprises steps of: determining a location for each spare latch in the macro; examining local clock buffers associated with the macro to locate any local clock buffers without a spare latch directly attached to clock nets driven by said local clock buffer; measuring a distance between each of the local clock buffers without spare latches and a closest spare latch; running statistics for the local clock buffers from the measuring step; and locating macros with inadequate spare latch placement using the statistics.

Abstract: A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times its commencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes.

Abstract: A method for determining gate array distribution includes steps or acts of: randomly placing a plurality of test boxes in a logic circuit layout; counting the number of fill cells in each of the plurality of test boxes; recording the count; grouping the plurality of test boxes into two groups: a first group with local clock buffers and a second group without local clock buffers; determining the fill cell percentage of each of the plurality of test boxes; and flagging the test boxes with a poor distribution of gate array cells.

Abstract: A multi-port electronic memory has a write through capability. Control features for enabling a write through path to an output and subsequently disabling without causing data errors due to design and technology variations are provided. Control features are especially beneficial for use with compilable SRAM books.