Abstract: Systems and methods for providing a seamless automatic repeat request (ARQ) stream are provided. The system can include a plurality of streaming servers, a load balancer, and an ARQ streaming service. The ARQ streaming service obtains encoded content segments and transmits the segments to a plurality of streaming servers. The plurality of streaming servers is configured to transmit the encoded content segments to a client computing device, and a load balancer is implemented between the client computing device and the plurality of streaming servers. When the client computing device sends a response message to the ARQ streaming service while receiving the encoded content segments from one of the plurality of streaming servers, the ARQ streaming service may identify a failure in the streaming server. The ARQ streaming service retransmits lost encoded content segments by switching the streaming path to another streaming server from the plurality of streaming servers.

Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

Abstract: Systems and methods for providing a seamless automatic repeat request (ARQ) stream are provided. The system can include a plurality of streaming servers, a load balancer, and an ARQ streaming service. The ARQ streaming service obtains encoded content segments and transmits the segments to a plurality of streaming servers. The plurality of streaming servers is configured to transmit the encoded content segments to a client computing device, and a load balancer is implemented between the client computing device and the plurality of streaming servers. When the client computing device sends a response message to the ARQ streaming service while receiving the encoded content segments from one of the plurality of streaming servers, the ARQ streaming service may identify a failure in the streaming server. The ARQ streaming service retransmits lost encoded content segments by switching the streaming path to another streaming server from the plurality of streaming servers.

Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.

Abstract: A specimen testing system has holders that hold a specimen for testing. The holders brace the specimen so that a load may be applied. A load applicator applies a load to the specimen at a location that is between the holders bracing the specimen. A user may adjust the load applicator until it applies the desired load to the specimen. If desired, a user may apply rotation to a specimen while it is experiencing a load by using a specimen rotation system. The user may continue to adjust the load applied to the specimen or continue to rotate the specimen during loading until the specimen fails.

Abstract: A system, method and article of manufacture are provided for account and customer creation in an online banking model. An application is received from a customer. The application includes information relating to the user and also documentation relating to the user. A first computer is utilized to create a profile for the customer based on the application received from the customer. The first computer is also utilized to create an account for the customer. Information relating to the created profile and account is transmitted from the first computer to a second computer where a notification is generated. The notification indicates that the account has been created. The notification is transmitted from the second computer to the customer utilizing a network.

Abstract: A grease interceptor includes a container having outer walls and a bottom connected to the outer walls, an inlet opening defined in one of the outer walls of the container, an outlet opening defined in an opposing outer wall of the container, an inlet baffle positioned adjacent the inlet opening, the inlet baffle comprising a protruding upper portion and a straight lower portion, a deflector positioned adjacent a bottom portion of the inlet baffle, a mid-wall baffle positioned at a substantially centered position along the longitudinal length of the container, and an exit baffle positioned adjacent the outlet opening. A method of removing grease from a wastewater stream through volume displacement is also disclosed.

Abstract: A level vial is provided that includes an outer structure disposed over the outer surface of an inner structure. The inner structure has an outer surface and interior surface. An internal cavity is defined by the interior surface. Laser markings are present in the inner structure on the outer surface and/or between the outer surface and interior surface of the inner structure. A liquid is sealed within the internal cavity. A method for manufacturing a level vial is also provided. The method includes providing an inner structure and molding a second structure over the outer surface of the inner structure. Radiation is transmitted through the second structure to form a marking on the inner structure. A liquid is sealed within the internal cavity.

Abstract: A level vial is provided that includes an outer structure disposed over the outer surface of an inner structure. The inner structure has an outer surface and interior surface. An internal cavity is defined by the interior surface. Laser markings are present in the inner structure on the outer surface and/or between the outer surface and interior surface of the inner structure. A liquid is sealed within the internal cavity. A method for manufacturing a level vial is also provided. The method includes providing an inner structure and molding a second structure over the outer surface of the inner structure. Radiation is transmitted through the second structure to form a marking on the inner structure. A liquid is sealed within the internal cavity.