Abstract: Methods for facilitating the synthesis of structured ASICs that are functionally equivalent to FPGAs make use of the synthesis of a user's logic design for the FPGA. Each of several relatively small parts of the user's logic as synthesized for the FPGA technology is resynthesized for the structured ASIC implementation. The resynthesis may handle different kinds of parts of the logic differently. For example, for a part for which an ASIC synthesis is already known and available in a library, the known ASIC synthesis may be retrieved from the library. More extensive resynthesis (including, for example, logic minimization and function packing) may be performed on other parts of the logic for which library syntheses are not available.

Abstract: A dedicated hardware block is provided for implementing crossbars and/or barrel shifters in programmable logic resources. Crossbar and/or barrel shifter circuitry may replace one or more rows, one or more columns, one or more rectangles, or any combination thereof of programmable logic regions on a programmable logic resource. The functionality of the crossbar and/or barrel shifter circuitry can further be improved by implementing time-multiplexing.

Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.

Abstract: Techniques for combining lookup tables on a programmable integrated circuit are provided. Lookup tables (LUTS) in a design for a programmable circuit can be combined into one mask if they implement the same function. Any two LUTs in a design can be compared to determine if they implement the same function by rearranging the input signals of one of the LUTs with respect to the input terminals of that LUT. Pairs of LUTs can be rejected if they do not share at least N common input signals, or if they have more than M unique input signals.

Abstract: Disclosed is a method an apparatus for selectively providing additional inputs into a logic block, such as a LAB of a PLD, carrying out a logic function requiring a relatively high number of inputs. A PLD in accordance with the present invention includes at least first and second LABs. A plurality of signal lines are capable of driving the second LAB and a plurality of output lines are driven by the first LAB. The PLD also includes a swap multiplexer (MUX) having a first selectable input capable of being driven by the output lines and a second selectable input capable of being driven by the signal lines. An output of the swap MUX is capable of driving the first LAB.

Abstract: A fracturable logic element includes a first, second, third, and fourth two-input lookup tables (2-LUTs). Each 2-LUT includes four memory elements. Each memory element is configured to hold one data bit. The fracturable logic element also includes a set of six inputs and a control circuit configured to operate in a first mode and a second mode. When the control circuit operates in the first mode, a first combinatorial output is generated using four of the set of six inputs and the first, second, third, and fourth 2-LUTs. When the control circuit operates in the second mode, a second combinatorial output is generated using a first subset of three of the set of six inputs and the first and second 2-LUTS. Additionally, when the control circuit operates in the second mode, a third combinatorial output is generated using a second subset of three of the set of six inputs and the third and fourth 2-LUTs, the first and second subsets being non-intersecting subsets of the set of six inputs.

Abstract: A dedicated hardware block is provided for implementing crossbars and/or barrel shifters in programmable logic resources. Crossbar and/or barrel shifter circuitry may replace one or more rows, one or more columns, one or more rectangles, or any combination thereof of programmable logic regions on a programmable logic resource. The functionality of the crossbar and/or barrel shifter circuitry can further be improved by implementing time-multiplexing.

Abstract: Additional circuitry is provided over a shared-LUT logic circuit to allow functions of different input characteristics to share a logic element which was conventionally illegal. More restrictive circuitry may be provided over a shared-LUT logic circuit to allow functions with particular input characteristics.

Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.

Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.

Abstract: The present invention is directed to methods and systems for improving the efficiency of livestock production using genetic information obtained from the animal. The methods of the invention comprise obtaining a genetic sample from an animal or embryo, determining the genotype of the animal or embryo with respect to specific quality traits, grouping animals with like genotypes, and optionally, further sub-grouping animals based on like phenotypes. Based on the genotype, an animal is treated in a particular way. For example, uniform feeding regimens are designed for a particular group so as to maximize feed efficiencies and accurately predict slaughter times among like animals possessing a desired quality trait.

Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.

Abstract: A self-locking, high-pressure stopper is disclosed. Also disclosed is a method of using the stopper. The stopper allows a branch pipe to be plugged from above ground using an elongated insertion tool. The self-locking stopper of the present invention includes a body having O-ring seals that is inserted into the branch pipe that is to be plugged. The self-locking stopper has outwardly biased locking tabs that are provided to engage a shoulder or step in the branching pipe in order to prevent the stopper from being pulled out, or pushed out by fluid pressure, once it is in place. The stopper system also includes a flanged insertion pipe used for inserting the stopper into the branch pipe. The stopper also has an adapter for engagement by an insertion tool that allows a user to insert the stopper from above ground.

Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.

Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.

Abstract: A system for performing regulated transactions is used with a network that is commonly accessible by a plurality of communication terminals. A gatekeeper, coupled to the network, permits access to the system only if authorization information, as indicated by an authorization signal received by the gatekeeper from a communication terminal via the network, complies with at least one predetermined criterion. The authorization information includes information independent of information supplied by a communication terminal user and independent of information indicative of a communication line coupled to the user's communication terminal. A host, coupled to the gatekeeper, receives a first signal from the user's communication terminal through the network and sends a second signal through the network to the user's communication terminal in response to the first signal.