Abstract: A central processing unit with dual boot capabilities is disclosed comprising an instruction memory further comprising a first and second memory area which are configured to be individually programmable, wherein first and second memory area can be assigned to an active memory from which instructions are executed and an inactive memory, respectively. The instruction set for the central processing unit comprises a dedicated instruction that allows to perform a swap from the an active memory area to an inactive memory area, wherein the swap is performed by executing the dedicated instruction in the active memory followed by a program flow change instruction in the active memory, whereupon the inactive memory becomes the new active memory and the active memory becomes the new inactive memory and execution of instructions continues in the new active memory.

Abstract: A central processing unit (CPU) having an interrupt unit for interrupting execution of instructions, a plurality context defining register sets, wherein each set of registers having the same number of CPU registers, a switching unit for coupling a selected register set within the CPU, wherein the switching unit switches to a predetermined register set of the plurality of context defining register sets upon occurrence of an exception, and a control register configured to control selection of a register set of the plurality of context defining register initiated by an instruction and further operable to indicate a currently used context.

Abstract: A digital processor has a default bus master having a highest priority in a default mode, a plurality of secondary bus masters having associated priorities, wherein the plurality of secondary bus masters have a predetermined priority relationship to each other, and a data space arbiter. The data space arbiter is programmable in a non-default mode to raise a priority of any of the secondary bus masters to have a priority higher than the priority of the default bus master while maintaining the predetermined priority relationship to only those secondary bus masters for which the priority level also has been raised above the priority of the default bus master.

Abstract: A central processing unit (CPU) having an interrupt unit for interrupting execution of instructions, a plurality context defining register sets, wherein each set of registers having the same number of CPU registers, a switching unit for coupling a selected register set within the CPU, wherein the switching unit switches to a predetermined register set of the plurality of context defining register sets upon occurrence of an exception, and a control register configured to control selection of a register set of the plurality of context defining register initiated by an instruction and further operable to indicate a currently used context.

Abstract: A central processing unit with dual boot capabilities is disclosed comprising an instruction memory further comprising a first and second memory area which are configured to be individually programmable, wherein first and second memory area can be assigned to an active memory from which instructions are executed and an inactive memory, respectively. The instruction set for the central processing unit comprises a dedicated instruction that allows to perform a swap from the an active memory area to an inactive memory area, wherein the swap is performed by executing the dedicated instruction in the active memory followed by a program flow change instruction in the active memory, whereupon the inactive memory becomes the new active memory and the active memory becomes the new inactive memory and execution of instructions continues in the new active memory.

Abstract: A digital processor with programmable exception processing latency, may have a central processing unit (CPU) of a digital processor, an exception controller coupled with the CPU, and a control register coupled with the CPU, wherein the control register is operable to set the operation mode of the CPU in at least one of two modes, wherein in the first mode the CPU has a fixed exception processing latency time, and in a second mode the CPU has a variable exception processing latency time.

Abstract: A processor may have at least one multiplier unit which can be controlled to operate in a signed, an unsigned, or a mixed sign mode; a multiplier unit mode decoder coupled with the multiplier unit which receives location information of a first and second operands, wherein the multiplier mode decoder controls the multiplier unit when in the mixed sign mode depending on the location information to operate in a signed mode, an unsigned mode, or a combined signed/unsigned mode.

Abstract: Trap flags and a pointer trap are associated with registers in a processor. Each trap flag indicates whether a corresponding register has been written with valid data. If not, the trap flag is set to indicate that the register corresponding to the trap flag contains invalid data. During instruction processing, the pointer trap receives control signals from instruction fetch/decode logic on the processor indicating an instruction being processed calls for a register to be used as a pointer. If the specified pointer register has its corresponding trap flag set, then the pointer trap indicates that a processing exception has occurred. The interrupt logic/exception processing logic then causes a trap interrupt service routine (ISR) to be executed in response to the exception. The ISR prevents errors from being introduced in the instruction processing due to invalid pointer values.

Abstract: A digital processor has a default bus master having a highest priority in a default mode, a plurality of secondary bus masters having associated priorities, wherein the plurality of secondary bus masters have a predetermined priority relationship to each other, and a data space arbiter. The data space arbiter is programmable in a non-default mode to raise a priority of any of the secondary bus masters to have a priority higher than the priority of the default bus master while maintaining the predetermined priority relationship to only those secondary bus masters for which the priority level also has been raised above the priority of the default bus master.

Abstract: A digital processor with programmable exception processing latency, may have a central processing unit (CPU) of a digital processor, an exception controller coupled with said CPU, and a control register coupled with said CPU, wherein the control register is operable to set the operation mode of said CPU in at least one of two modes, wherein in the first mode the CPU has a fixed exception processing latency time, and in a second mode the CPU has a variable exception processing latency time.

Abstract: A processor may have at least one multiplier unit which can be controlled to operate in a signed, an unsigned, or a mixed sign mode; a multiplier unit mode decoder coupled with the multiplier unit which receives location information of a first and second operands, wherein the multiplier mode decoder controls the multiplier unit when in the mixed sign mode depending on the location information to operate in a signed mode, an unsigned mode, or a combined signed/unsigned mode.

Abstract: A system and method for overflow and saturation processing during accumulator operations that reduces the error in a saturation operation. Upon overflow, additional guard bits used in conjunction with an accumulator allow a user to continue processing without any error in the values used in computations following the overflow. A saturation condition can be detected following the overflow the appropriate maximum value stored in the accumulator upon detecting saturation.

Abstract: A method and a processor for processing a power mode instruction are provided. The power mode instruction itself includes up to five different sleep modes and one run mode, each for initiating a clock source change or inhibit. This instruction may be executed in one processor cycle and with one power mode instruction employing clock transition logic within the processor to initiate a switch to the clock source configuration specified by a literal, such as a 3-bit literal. Operand may be written the register of clock transition logic to define an exit state for a sleep mode.

Abstract: A method and processor for multiplying two maximally negative fractional numbers to produce a 32-bit result are provided. Operands are fetched from a source location for operation of a multiplication operation. Result outputs corresponding to a maximally negative result are detected. The detection of a maximally negative result indicates that the operands are two maximally negative fractional numbers. Maximally negative results are corrected to produce a maximally positive result. Result output are fractionally aligned and sign extended for accumulation in an accumulator.

Abstract: A method and processor for multiplication operation instruction processing are provided. Multiplication operation instructions are executed on source operands in data memory locations. The multiplication operation instructions are provided to perform complex multiplication operations. The multiplication operation instructions may generate the square of a multiplication source operand and generate the difference of a subtrahend source operand and a minuend source operand simultaneously. The square is output to a target accumulator specified in the multiplication operation instruction. The difference is output to a difference register specified in the multiplication operation instruction. In the alternative, the multiplication operation instructions may generate the sum of the square of multiplication source operand and an addition operand as well as generate the difference of a subtrahend source operand and a minuend source operand simultaneously.

Abstract: A hardware based modulo addressing scheme is described that is fast and makes efficient use of logic. The scheme uses a subtractor, multiplexers and AND/OR logic to produce modulo addresses to address, for example, a circular buffer in a memory. The buffer is defined by the user based on start and end addresses and an offset value. The offset may be positive or negative and may be greater than one.

Abstract: A method and a processor for processing a power mode instruction are provided. The power mode instruction itself includes up to five different sleep modes and one run mode, each for initiating a clock source change or inhibit. This instruction may be executed in one processor cycle and with one power mode instruction employing clock transition logic within the processor to initiate a switch to the clock source configuration specified by a literal, such as a 3-bit literal. Operand may be written the register of clock transition logic to define an exit state for a sleep mode.

Abstract: An instruction set is provided that features ninety four instructions and various address modes to deliver a mixture of flexible micro-controller like instructions and specialized digital signal processor (DSP) instructions that execute from a single instruction stream.

Abstract: A processor has a native word width of multiples of a byte width. The processor may, nonetheless, process, store and retrieve data in word or byte widths depending on the mode of an instruction directing the processing. Instructions may assume either a word or a byte mode. In the word mode, the instruction causes the processor to read, store and operate on word width data. In the byte mode, the instruction causes the processor to read, store and operate on byte data where the byte is specified based on upper/lower byte bits in the instruction. This architecture permits a new generation of processor having word widths of more than one byte to be backward compatible with software written for byte width processors.

Abstract: A processor configuration for processing multi-precision shift instructions is provided. The multi-precision shift instructions are executed following a previous shift instruction of the same increment, such as a logical or arithmetic left or right shift operation. The first shift instruction shifts a first memory word by the shift increment and stores this shifted value into memory. The second, and any subsequent, multi-precision shift instruction shifts the next memory word by the shift increment and concatenates the bits shifted out of the previously shifted memory word into bit positions of the memory word presently being shifted. This concatenated value is then stored back to memory and forms another part of the multi-precision shifted value.