Abstract: Bit operation instructions such as find first bit instructions are provided. The instructions themselves include four instructions for returning a value corresponding to a bit position that stores the first zero or the first one in a memory location beginning from the left or right side of a data word depending on the instruction. Two additional instructions find the first bit change from the left or the right side of a memory location. The instructions operate on data specified in a source register and return a result to a destination register. The source and destination registers may store the data directly or may store pointers to the data. In addition, the instructions may specify the source data as word or byte data.

Abstract: A hardware based modulo addressing scheme is described that is fast and makes efficient use of logic. The scheme uses a subtractor, multiplexers and AND/OR logic to produce modulo addresses to address, for example, a circular buffer in a memory. The buffer is defined by the user based on start and end addresses and an offset value. The offset may be positive or negative and may be greater than one.

Abstract: A method and processor for multiplication operation instruction processing are provided. Multiplication operation instructions are executed on source operands in data memory locations. The multiplication operation instructions are provided to perform complex multiplication operations. The multiplication operation instructions may generate the square of a multiplication source operand and generate the difference of a subtrahend source operand and a minuend source operand simultaneously. The square is output to a target accumulator specified in the multiplication operation instruction. The difference is output to a difference register specified in the multiplication operation instruction. In the alternative, the multiplication operation instructions may generate the sum of the square of multiplication source operand and an addition operand as well as generate the difference of a subtrahend source operand and a minuend source operand simultaneously.

Abstract: A system and method for overflow and saturation processing during accumulator operations that reduces the error in a saturation operation. Upon overflow, additional guard bits used in conjunction with an accumulator allow a user to continue processing without any error in the values used in computations following the overflow. A saturation condition can be detected following the overflow the appropriate maximum value stored in the accumulator upon detecting saturation.

Abstract: A method and processor for multiplying two maximally negative fractional numbers to produce a 32-bit result are provided. Operands are fetched from a source location for operation of a multiplication operation. Result outputs corresponding to a maximally negative result are detected. The detection of a maximally negative result indicates that the operands are two maximally negative fractional numbers. Maximally negative results are corrected to produce a maximally positive result. Result output are fractionally aligned and sign extended for accumulation in an accumulator.

Abstract: Method and apparatus for providing erasing and programming protection of an EEPROM (22) to significantly reduce the possibility of unintentional erasing or programming of the EEPROM (22). In one embodiment, a read access of a block protect value (111) is a requirement for enabling the EEPROM charge pump (78). The block protect value (111) may be located in the EEPROM array (22) itself. In one embodiment, an externally provided signal (24) must be provided to an integrated circuit (10) in order to enable a write access to modify the block protect value (111). In one embodiment, a charge pump enable value (103) is provided to enable or disable operation of the charge pump (78). Thus, a combination of hardware and software protection is provided for an EEPROM (22), including protection for enabling of a charge pump (78).

Abstract: Method and apparatus in a data processing system (10) for determining wait states on a per cycle basis. The present invention provides a wait state value (39) to a data processing system (10) indicating the number of wait states for each bus cycle. In one embodiment, a wait state pulse (81) is provided by data processing system (10), during which the wait state value (39) is provided to data processing system (10) by way of data bus (82). In response to the wait state value (39), data processing system (10) inserts a number of wait states corresponding to the wait state value (39) during the present bus cycle. In one embodiment of the present invention, a chip select signal (73) is combined with a portion of the address (83) to further partition the address range of the chip select signal (73).

Abstract: A data processing system providing an extensible register and method thereof. A new CPU has an extensible index register. The new CPU is object code compatible with the old CPU having an 8-bit index register, yet the index register of the new CPU can be effectively extended to 16 bits when new instructions are used. As a consequence, the user is able to make the choice between using assembly code software written for the old CPU and having the functionality of an 8-bit index register, or writing new assembly code software for the new CPU and having the functionality of a 16-bit index register.

Abstract: A data processor (20) includes a nonvolatile memory system (25) which stores not only normal program memory (31), but also mask option bits (32), within a common array (30) of nonvolatile memory cells. A control circuit (40) of the nonvolatile memory system (25) detects when a central processing unit (21) is accessing the program memory (31). In response to either an end of reset signal or a refresh request signal, the control circuit (40) copies the mask option bits (32) into a volatile mask option register (44) only when the central processing unit (21) is not accessing the program memory (31). Otherwise, the control circuit (40) holds off the access to the mask option bits (32). The mask option register (44) provides signals to various circuits (28) to control their operation. Thus, the mask option bits (32) may be stored in nonvolatile form in the same array (30) as the program memory (31), enhancing reliability and reducing integrated circuit size.

Abstract: A timer (28) uses two output-compare timer channels to form a buffered pulse width modulator. A first register (62) and a second register are provided to store a first pulse width value and a second register (66), respectively. When the first register (62) is written to, a select control circuit (68) provides the first pulse width value stored therein to a channel input/output circuit (70). When the second register (66) is written to, the select control circuit (68) provides the second pulse width value stored therein to the channel input/output circuit (70). The select control circuit (68) provides one of the first and second pulse width values such that the signal output by the channel input/output circuit (70) is not erroneous. By writing a new pulse width value to a register associated with an unused channel, the pulse width modulation function is buffered.

Abstract: A data processing system (10) having address pins (30), data pins (31), control pins (32), chip select pins (33), and other pins (34). For bus cycles of an instruction which do not require use of an external address bus (35), the values driven by the address pins (30) are "frozen" in their previous logic state. The previous logic state is determined by the most recent value driven by address pins (30) during a bus cycle that required use of the external address bus (35). Data pins (31) may be "frozen" in the same manner as address pins (30). Control pins 32, chip select pins 33, and other pins 34 may be driven to their respective inactive logic states. The goal is to reduce noise and power consumption by reducing the voltage level switching taking place on external conductors (35-39).

Abstract: A memory expansion scheme is provided which permits a program to automatically cross memory bank boundaries, without user intervention. A memory bank address register stores a value corresponding to a selected memory bank (i.e. Bank 0), in a 4-bit subfield (K-Field). In the preferred embodiment, the K-Field is implemented using six (6) bank number registers, each of which is coupled to the corresponding address register, to form a 20-bit (extended) logical address. During an effective address calculation, in the index addressing mode, a 16-bit logical offset address, stored in an offset register, is added to the 20-bit (extended) logical address, by an adder in the ALU. The adder transfers a 20-bit physical address onto an address bus, via an address buffer. When the calculated address crosses a memory bank boundary, the upper four (4) address bits (A.sub.16 -A.sub.19) are automatically updated, thereby enabling the program to cross a memory bank boundary without user intervention.