Patents by Inventor Michael Ignatowski

Michael Ignatowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12248516
    Abstract: An accelerator device includes a first processing unit to access a structure of a graph dataset, and a second processing unit coupled with the first processing unit to perform computations based on data values in the graph dataset.
    Type: Grant
    Filed: February 8, 2024
    Date of Patent: March 11, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ganesh Dasika, Michael Ignatowski, Michael J Schulte, Gabriel H Loh, Valentina Salapura, Angela Beth Dalton
  • Patent number: 12197735
    Abstract: A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: January 14, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vignesh Adhinarayanan, Michael Ignatowski, Hyung-Dong Lee
  • Publication number: 20240419735
    Abstract: An accelerator device includes a first processing unit to access a structure of a graph dataset, and a second processing unit coupled with the first processing unit to perform computations based on data values in the graph dataset.
    Type: Application
    Filed: February 8, 2024
    Publication date: December 19, 2024
    Inventors: Ganesh Dasika, Michael Ignatowski, Michael J. Schulte, Gabriel H. Loh, Valentina Salapura, Angela Beth Dalton
  • Patent number: 12124531
    Abstract: A processing device including a plurality of clusters of processor cores and a method for use in the processing device is disclosed. Each processor core in a cluster of processor cores is in communication with the other processor cores in the cluster and at least one processor core of each cluster is in communication with at least a processor core of a different cluster of processor cores. Each processor core is configured to store a product of a portion of a first matrix and a first portion of a second matrix in the memory, and store a product of the portion of the first matrix and a second portion of the second matrix in the memory, where the second portion of the second matrix is received from a processor core in the cluster of processor cores.
    Type: Grant
    Filed: April 7, 2023
    Date of Patent: October 22, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shaizeen Aga, Nuwan Jayasena, Allen H. Rush, Michael Ignatowski
  • Publication number: 20240329846
    Abstract: A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Vignesh Adhinarayanan, Michael Ignatowski, Hyung-Dong Lee
  • Publication number: 20240329847
    Abstract: A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Vignesh Adhinarayanan, Michael Ignatowski, Hyung-Dong Lee
  • Patent number: 12086418
    Abstract: A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: September 10, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vignesh Adhinarayanan, Michael Ignatowski, Hyung-Dong Lee
  • Publication number: 20240273040
    Abstract: Multi-stack compute chip and memory architecture is described. In accordance with the described techniques, a package includes a plurality of computing stacks, and each computing stack includes at least one compute chip and a memory. The package also includes one or more interconnects that couple the computing stacks to at least one other computing stack for sharing the memory in a coherent fashion across the plurality of computing stacks.
    Type: Application
    Filed: December 20, 2023
    Publication date: August 15, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Michael Ignatowski, Michael J. Schulte, Gabriel Hsiuwei Loh
  • Publication number: 20240088099
    Abstract: Memory stacks having substantially vertical bitlines, and chip packages having the same, are disclosed herein. In one example, a memory stack is provided that includes a first memory IC die and a second memory IC die. The second memory IC die is stacked on the first memory IC die. Bitlines are routed through the first and second IC dies in a substantially vertical orientation. Wordlines within the first memory IC die are oriented orthogonal to the bitlines.
    Type: Application
    Filed: June 28, 2023
    Publication date: March 14, 2024
    Inventors: Divya Madapusi Srinivas PRASAD, Vignesh ADHINARAYANAN, Michael IGNATOWSKI, Hyung-Dong LEE
  • Publication number: 20240087636
    Abstract: Dynamic memory operations are described. In accordance with the described techniques, a system includes a stacked memory and one or more memory monitors configured to monitor conditions of the stacked memory. A system manager is configured to receive the monitored conditions of the stacked memory from the one or more memory monitors, and dynamically adjust operation of the stacked memory based on the monitored conditions. In one or more implementations, a system includes a memory and at least one register configured to store a ranking for each of a plurality of portions of the memory. Each respective ranking is determined based on an associated retention time of the respective portion of the memory. A memory controller is configured to dynamically refresh the portions of the memory at different times based on the ranking for each of the plurality of portions of the memory stored in the at least one register.
    Type: Application
    Filed: June 12, 2023
    Publication date: March 14, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Divya Madapusi Srinivas Prasad, Michael Ignatowski
  • Publication number: 20240087632
    Abstract: A memory device includes memory cells. A memory cell of the memory cells includes gate circuitry, a first capacitor, and a second capacitor. The gate circuitry is connected to a wordline and a bitline. The first capacitor is connected to the gate circuitry and a first drive line. The second capacitor is connected to the gate circuitry and a second drive line.
    Type: Application
    Filed: June 29, 2023
    Publication date: March 14, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Divya Madapusi Srinivas PRASAD, Michael IGNATOWSKI, Niti MADAN
  • Publication number: 20240088098
    Abstract: Disclosed wherein stacked memory dies that utilize a mix of high and low operational temperature memory and non-volatile based memory dies, and chip packages containing the same. High temperature memory dies, such as those using non-volatile memory (NVM) technologies are in a memory stack with low temperature memory dies, such as those having volatile memory technologies. In some cases, the high temperature memory technologies could be used together, in some cases, on the same IC die as logic circuitry. In one example, a memory stack is provided that include a first memory IC die having high temperature memory circuitry, such as non-volatile memory, stacked below a second memory IC die. The second memory IC die has high temperature memory circuitry, such as volatile memory circuitry.
    Type: Application
    Filed: May 19, 2023
    Publication date: March 14, 2024
    Inventors: Divya Madapusi Srinivas PRASAD, Niti MADAN, Michael IGNATOWSKI, Hyung-Dong LEE
  • Publication number: 20240087667
    Abstract: Error correction for stacked memory is described. In accordance with the described techniques, a system includes a plurality of error correction code engines to detect vulnerabilities in a stacked memory and coordinate at least one vulnerability detected for a portion of the stacked memory to at least one other portion of the stacked memory.
    Type: Application
    Filed: August 29, 2023
    Publication date: March 14, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Divya Madapusi Srinivas Prasad, Michael Ignatowski, Gabriel Loh
  • Publication number: 20240087631
    Abstract: A memory device includes a memory circuitry includes a first transmission grate, a first capacitor, a second transmission gate, and a second capacitor. The first transmission gate includes a first transistor connected between a first node and a second node. The first transistor having a gate terminal connected to a first clock node. The first clock node configured to receive a first clock signal. The first capacitor is connected between the second node and a first voltage node. The first capacitor is a ferroelectric capacitor. The second transmission gate includes a second transistor connected between the second node and a third node. The second transistor has a gate terminal connected to the first clock node. The second capacitor is connected between the third node and a second voltage node.
    Type: Application
    Filed: June 29, 2023
    Publication date: March 14, 2024
    Inventors: Divya Madapusi Srinivas PRASAD, Michael IGNATOWSKI
  • Patent number: 11921784
    Abstract: An accelerator device includes a first processing unit to access a structure of a graph dataset, and a second processing unit coupled with the first processing unit to perform computations based on data values in the graph dataset.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: March 5, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ganesh Dasika, Michael Ignatowski, Michael J Schulte, Gabriel H Loh, Valentina Salapura, Angela Beth Dalton
  • Patent number: 11874739
    Abstract: A memory module includes one or more programmable ECC engines that may be programed by a host processing element with a particular ECC implementation. As used herein, the term “ECC implementation” refers to ECC functionality for performing error detection and subsequent processing, for example using the results of the error detection to perform error correction and to encode corrupted data that cannot be corrected, etc. The approach allows an SoC designer or company to program and reprogram ECC engines in memory modules in a secure manner without having to disclose the particular ECC implementations used by the ECC engines to memory vendors or third parties.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: January 16, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sudhanva Gurumurthi, Vilas Sridharan, Shaizeen Aga, Nuwan Jayasena, Michael Ignatowski, Shrikanth Ganapathy, John Kalamatianos
  • Publication number: 20230350830
    Abstract: An apparatus and method for performing memory operations in memory stacks comprising receiving a memory operation request at a first memory controller, where the first memory controller is in included in a first logic die in communication with a first memory die of a first memory technology, from a processor via a first bus. The method further comprising, on a condition that the memory operation request is associated with a second memory technology, communicating the memory operation request to a second memory controller via a side bus, where the second memory controller is included in a second logic die in communication with a second memory die of the second memory technology, and, on a condition that the memory operation request is associated with the first memory technology, performing the memory operation request. The first and second logic dies and the first and second memory dies being stacked on the processor.
    Type: Application
    Filed: March 13, 2023
    Publication date: November 2, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Dmitri Yudanov, Michael Ignatowski
  • Publication number: 20230244751
    Abstract: A processing device is provided which comprises memory configured to store data and a plurality of processor cores in communication with each other via first and second hierarchical communication links. Processor cores of a first hierarchical processor core group are in communication with each other via the first hierarchical communication links and are configured to store, in the memory, a sub-portion of data of a first matrix and a sub-portion of data of a second matrix. The processor cores are also configured to determine a product of the sub-portion of data of the first matrix and the sub-portion of data of the second matrix, receive, from another processor core, another sub-portion of data of the second matrix and determine a product of the sub-portion of data of the first matrix and the other sub-portion of data of the second matrix.
    Type: Application
    Filed: April 7, 2023
    Publication date: August 3, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Shaizeen Aga, Nuwan Jayasena, Allen H. Rush, Michael Ignatowski
  • Patent number: 11709745
    Abstract: A method includes, in response to a memory error indication indicating an uncorrectable error in a faulted segment, associating in a remapping table the faulted segment with a patch segment in a patch memory region, and in response to receiving from a processor a memory access request directed to the faulted segment, servicing the memory access request from the patch segment by performing the requested memory access at the patch segment based on a patch segment address identifying the location of the patch segment. The patch segment address is determined from the remapping table and corresponds to a requested memory address specified by the memory access request.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: July 25, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sergey Blagodurov, Michael Ignatowski, Vilas Sridharan
  • Patent number: 11640444
    Abstract: A processing device is provided which comprises memory configured to store data and a plurality of processor cores in communication with each other via first and second hierarchical communication links. Processor cores of a first hierarchical processor core group are in communication with each other via the first hierarchical communication links and are configured to store, in the memory, a sub-portion of data of a first matrix and a sub-portion of data of a second matrix. The processor cores are also configured to determine a product of the sub-portion of data of the first matrix and the sub-portion of data of the second matrix, receive, from another processor core, another sub-portion of data of the second matrix and determine a product of the sub-portion of data of the first matrix and the other sub-portion of data of the second matrix.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: May 2, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shaizeen Aga, Nuwan Jayasena, Allen H. Rush, Michael Ignatowski