Abstract: Computer memory management systems and methods are provided in which data block buffering and priority scheduling protocols are utilized in compressed memory systems to mask the latency associated with memory reorganization work following access to compressed main memory. In particular, data block buffers and priority scheduling protocols are implemented to delay and prioritize memory reorganization work to allow resources to be used for serving new memory access requests and other high priority commands.

Abstract: A multiple-core processor supporting multiple instruction set architectures provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). The processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. The multiple cores may share a common first level cache and be mutually-exclusively selected for operation, or multiple level-one caches may be provided, one associated with each of the cores and the cores operated as needed, including simultaneous execution of disparate ISAs. A hypervisor controls operation of the cores and locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received.

Abstract: Multiple instruction set architectures are supported in a system that provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). A processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. A hypervisor controls operation of the cores, locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received. The ISA may be specified by a particular operating system and/or application program requirements.

Abstract: An apparatus is provided for modeling queuing systems with highly variable traffic arrival rates. The apparatus includes means to associate a value with a pattern of highly variable arrival rates that is simple and intuitive, and a means to accurately model queuing delays in systems that are characterized by bursts of arrival activity. The queuing delay is determined by a sum of queuing delays after first applying a weighting factor to the queuing delay based upon a random arrival rate, and a different weighting factor to the queuing delay based upon a bursty variable arrival rate. The weighting factors are variants of the server utilization. The model facilitates specification of server characteristics and configurations to meet response time metrics.

Abstract: A method, system, and computer program product are disclosed for dynamically managing power in a microprocessor chip that includes physical hardware elements within the microprocessor chip. A process is selected to be executed. Hardware elements that are necessary to execute the process are then identified. The power in the microprocessor chip is dynamically altered by altering a present power state of the hardware elements that were identified as being necessary.

Abstract: A stacked semiconductor chip comprising multiple unit chips contains multiple instances of a first chip component that have a low yield and are distributed among the multiple unit chips. An instance of the first chip component within a first unit chip is logically paired with at least another instance of the first chip component within at least another unit chip so that the combination of the multiple instances of the first chip component across the multiple unit chips constitute a functional block providing the functionality of a fully functional instance of the first chip component. The stacked semiconductor chip may include multiple instances of a second chip component having a high yield and distributed across the multiple unit chips. Multiple low yield components constitute a functional block providing an enhanced overall yield, while high yield components are utilized to their full potential functionality.

Abstract: A multiprocessor computer system has a plurality of processing nodes which use processor state information to determine which coherent caches in the system are required to examine a coherency transaction produced by a single originating processor's storage request. A node of the computer has dynamic coherency boundaries such that the hardware uses only a subset of the total processors in a large system for a single workload at any specific point in time and can optimize the cache coherency as the supervisor software or firmware expands and contracts the number of processors which are being used to run any single workload. Multiple instances of a node can be connected with a second level controller to create a large multiprocessor system. The node controller uses the mode bits to determine which processors must receive any given transaction that is received by the node controller.

Abstract: A method, system, and computer program product are disclosed for dynamically managing power in a microprocessor chip that includes physical hardware elements within the microprocessor chip. A process is selected to be executed. Hardware elements that are necessary to execute the process are then identified. The power in the microprocessor chip is dynamically altered by altering a present power state of the hardware elements that were identified as being necessary.

Abstract: A method, system, and computer program product are disclosed for dynamically managing power in a microprocessor chip that includes physical hardware elements within the microprocessor chip. A process is selected to be executed. Hardware elements that are necessary to execute the process are then identified. The power in the microprocessor chip is dynamically altered by altering a present power state of the hardware elements that were identified as being necessary.

Abstract: An apparatus are provided for modeling queuing systems with highly variable traffic arrival rates. The apparatus includes a means to associate a value with a pattern of highly variable arrival rates that is simple and intuitive, and a means to accurately model queuing delays in systems that are characterized by bursts of arrival activity. The queuing delay is determined by a sum of queuing delays after first applying a weighting factor to the queuing delay based upon a random arrival rate, and a different weighting factor to the queuing delay based upon a bursty variable arrival rate. The weighting factors are variants of the server utilization. The model facilitates specification of server characteristics and configurations to meet response time metrics.

Abstract: A multiprocessor computer system has a plurality of processing nodes which use processor state information to determine which coherent caches in the system are required to examine a coherency transaction produced by a single originating processor's storage request. A node of the computer has dynamic coherency boundaries such that the hardware uses only a subset of the total processors in a large system for a single workload at any specific point in time and can optimize the cache coherency as the supervisor software or firmware expands and contracts the number of processors which are being used to run any single workload. Multiple instances of a node can be connected with a second level controller to create a large multiprocessor system. The node controller uses the mode bits to determine which processors must receive any given transaction that is received by the node controller.

Abstract: A method are provided for modeling queuing systems with highly variable traffic arrival rates. The method includes a means to associate a value with a pattern of highly variable arrival rates that is simple and intuitive, and a means to accurately model queuing delays in systems that are characterized by bursts of arrival activity. The queuing delay is determined by a sum of queuing delays after first applying a weighting factor to the queuing delay based upon a random arrival rate, and a different weighting factor to the queuing delay based upon a bursty variable arrival rate. The weighting factors are variants of the server utilization. The model facilitates specification of server characteristics and configurations to meet response time metrics.

Abstract: Computer memory management systems and methods are provided in which data block buffering and priority scheduling protocols are utilized in compressed memory systems to mask the latency associated with memory reorganization work following access to compressed main memory. In particular, data block buffers and priority scheduling protocols are implemented to delay and prioritize memory reorganization work to allow resources to be used for serving new memory access requests and other high priority commands.

Abstract: A multiple-core processor supporting multiple instruction set architectures provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). The processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. The multiple cores may share a common first level cache and be mutually-exclusively selected for operation, or multiple level-one caches may be provided, one associated with each of the cores and the cores operated as needed, including simultaneous execution of disparate ISAs. A hypervisor controls operation of the cores and locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received.

Abstract: The present invention discloses a method, system and article of manufacture for performing analytic modeling on a computer system by handling a plurality of predefined system criteria directed to a modeled computer system. The present invention provides means for the user of an analytic model to specify (i.e. enable) any number of predefined system criteria that must all be simultaneously satisfied. The modeling methodology uses a variation of the well-known Mean Value Analysis technique in its calculations. Response times, resource utilizations, and resource queue lengths are initially estimated for a small user arrival rate. An iterative method is used to gradually increase the user arrival rate by a constant value. For each iteration, response times, resource utilizations, and resource queue lengths are calculated. Then for all the criteria, which have been enabled, it is checked to see if the value limits specified for those criteria have exceeded.

Abstract: A method, system, and computer program product are disclosed for dynamically managing power in a microprocessor chip that includes physical hardware elements within the microprocessor chip. A process is selected to be executed. Hardware elements that are necessary to execute the process are then identified. The power in the microprocessor chip is dynamically altered by altering a present power state of the hardware elements that were identified as being necessary.

Abstract: An apparatus and method are provided for modeling queuing systems with highly variable traffic arrival rates. The apparatus and method include a means to associate a value with a pattern of highly variable arrival rates that is simple and intuitive, and a means to accurately model queuing delays in systems that are characterized by bursts of arrival activity. The queuing delay is determined by a sum of queuing delays after first applying a weighting factor to the queuing delay based upon a random arrival rate, and a different weighting factor to the queuing delay based upon a bursty variable arrival rate. The weighting factors are variants of the server utilization. The model facilitates specification of server characteristics and configurations to meet response time metrics.

Abstract: A multiprocessor computer system has a plurality of processing nodes which use processor state information to determine which coherent caches in the system are required to examine a coherency transaction produced by a single originating processor's storage request. A node of the computer has dynamic coherency boundaries such that the hardware uses only a subset of the total processors in a large system for a single workload at any specific point in time and can optimize the cache coherency as the supervisor software or firmware expands and contracts the number of processors which are being used to run any single workload. Multiple instances of a node can be connected with a second level controller to create a large multiprocessor system. The node controller uses the mode bits to determine which processors must receive any given transaction that is received by the node controller.

Abstract: A method, system and article of manufacture for estimating the performance of a computer system are provided. Initially, a business pattern representative of the expected usage of the computer system is identified. Then, for each parameter associated with each predefined script, which corresponds to the identified business pattern, a value is established. The computer system hardware characteristics and performance objectives are identified next. The performance estimate is then calculated utilizing the established parameter values, identified hardware characteristics and performance objectives. To calculate the performance estimate, the script measurements data is read from a table of previously measured values, and a weighted average number of page visits per user, a weighted average visit rate and a weighted average service time for each target device in the computer system are calculated.

Abstract: The present invention discloses a method, system and article of manufacture for performing analytic modeling on a computer system by handling a plurality of predefined system criteria directed to a modeled computer system. The present invention provides means for the user of an analytic model to specify (i.e. enable) any number of predefined system criteria that must all be simultaneously satisfied. The modeling methodology uses a variation of the well-known Mean Value Analysis technique in its calculations. Response times, resource utilizations, and resource queue lengths are initially estimated for a small user arrival rate. An iterative method is used to gradually increase the user arrival rate by a constant value. For each iteration, response times, resource utilizations, and resource queue lengths are calculated. Then for all the criteria, which have been enabled, it is checked to see if the value limits specified for those criteria have exceeded.