Patents by Inventor Michael J. Berman

Michael J. Berman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6739953
    Abstract: According to one embodiment, a method of planarizing of a surface of a semiconductor substrate is provided. A copper layer is inlaid in a dielectric layer of the substrate. The semiconductor substrate is disposed opposite to a polishing pad and relative movement provided between the pad and the substrate. An electrolytic slurry containing abrasive particles is flowed over the substrate or the pad. A voltage is applied between the polishing pad and the substrate to perform electropolishing of the substrate. The rate of chemical mechanical polishing is controlled by the down force applied to a polishing head urging the substrate against the polishing pad.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: May 25, 2004
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Berman, Steven E. Reder
  • Patent number: 6722948
    Abstract: A modification to a chemical mechanical polishing conditioner of a type having a member with a conditioning surface adapted to apply a force to and condition a polishing pad. The conditioner includes at least one sensor disposed within the member, where the at least one sensor is adapted to sense at least one of an amount of the force applied to the polishing pad and a uniformity across the member of the force applied to the polishing pad. In this manner, the force applied by the conditioner to the pad, and the uniformity of the force applied by the conditioner to the pad, can be sensed. These sensed forces can be monitored, reported, and controlled, thus providing a better controlled chemical mechanical polishing process.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: April 20, 2004
    Assignee: LSI Logic Corporation
    Inventor: Michael J. Berman
  • Publication number: 20040069407
    Abstract: A method of detecting contamination on a backside of a semiconductor wafer includes the steps of positioning the backside of the wafer in contact with a detection surface of a contaminant sensor, and detecting deformation of the detection surface of the contaminant sensor. The contaminant sensor may be incorporated into a fabrication device such as a wafer handling device, or can be utilized in the construction of a stand-alone device. An apparatus for detecting contamination on the backside of a semiconductor wafer is also disclosed.
    Type: Application
    Filed: July 28, 2003
    Publication date: April 15, 2004
    Inventors: Michael J. Berman, George E. Bailey, Rennie G. Barber
  • Publication number: 20040067421
    Abstract: A mask for use in a photolithographic process. The mask includes a plate or substrate having first and second opposite surfaces, a first image on the first surface of the substrate and a second image on the second surface of the substrate. When the mask is used in a photolithographic process, energy is reflected by the first image prior to entering the substrate and energy is reflected by the second image after passing through the substrate.
    Type: Application
    Filed: October 7, 2002
    Publication date: April 8, 2004
    Inventors: Michael J. Berman, George E. Bailey
  • Patent number: 6691872
    Abstract: A method for producing cosmetic samplers that incorporates the genuine cosmetic through the use of bulk thin film application techniques such as extrusion or spray technology. The method comprises first applying a cosmetic slurry to a base substrate and then attaching a cover sheet by means of an adhesive on either wide-web offset or label equipment.
    Type: Grant
    Filed: July 7, 2000
    Date of Patent: February 17, 2004
    Assignee: Aki, Inc.
    Inventors: Michael J. Berman, William Deierlein, Michael Parrotta, Phillip Cameron, Allan Cameron, III
  • Publication number: 20040018448
    Abstract: A method to improve the resolution of a photolithography system by using one or more coupling layers between a photo resist and an anti-reflective coating. The coupling layer(s) compensate for a mis-match in indexes of reflection between the photo resist and anti-reflective coating and minimize the amount of energy which is reflected back into the photo resist, thereby improving the quality of the resulting image which is formed on the photo resist during the process.
    Type: Application
    Filed: July 29, 2002
    Publication date: January 29, 2004
    Inventors: Michael J. Berman, George E. Bailey
  • Publication number: 20030211811
    Abstract: A substrate carrier having a deformable surface for receiving a substrate. Non annular pressure application zones apply pressure to the deformable surface, and addressable transducers within the pressure application zones receive a signal and applying a selectable amount of pressure in response to the signal. In this manner, the amount of pressure provided by the substrate carrier differs from one portion of the substrate to another in a selectable manner. Thus, the pressure applied to the substrate can be tailored to the non uniform thickness of the layer that is being thinned. In other words, portions of the substrate where the layer is thicker can be pressed upon with a greater force by the substrate carrier, thus urging the substrate more forcefully into the polishing pad in those portions, and thereby removing material from the layer at a greater rate of speed in those portions.
    Type: Application
    Filed: May 10, 2002
    Publication date: November 13, 2003
    Inventors: Michael J. Berman, Steven E. Reder
  • Patent number: 6630411
    Abstract: A system, apparatus and/or method is provided for removing water vapor from a wafer processing chamber generated as a byproduct of wafer processing. A water vapor trap is used to collect the water vapor byproduct from the processing chamber interior. The water vapor trap has at least a portion thereof in communication with an interior of the processing chamber for collection of the water vapor and another portion thereof in communication with an exterior of the processing chamber. The portions are movable with respect to the interior and exterior of the processing chamber such that the portions may switch places. This allows the processing chamber to be in at least a substantially continuous mode of operation while still providing for the removal of water vapor byproduct via the water vapor trap. The “used” portion of the water vapor trap is regenerated while the “clean” portion is collecting water vapor.
    Type: Grant
    Filed: May 7, 2002
    Date of Patent: October 7, 2003
    Assignee: LSI Logic Corporation
    Inventors: Robert D. Broyles, Michael J. Berman
  • Patent number: 6627466
    Abstract: A method of detecting contamination on a backside of a semiconductor wafer includes the steps of positioning the backside of the wafer in contact with a detection surface of a contaminant sensor, and detecting deformation of the detection surface of the contaminant sensor. The contaminant sensor may be incorporated into a fabrication device such as a wafer handling device, or can be utilized in the construction of a stand-alone device. An apparatus for detecting contamination on the backside of a semiconductor wafer is also disclosed.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: September 30, 2003
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Berman, George E. Bailey, Rennie G. Barber
  • Patent number: 6464566
    Abstract: An apparatus for planarizing a surface of a semiconductor wafer includes a wafer support configured to receive the semiconductor wafer so that the surface of the semiconductor wafer projects from the wafer support. The apparatus also includes a polishing member configured in the form of an endless unitary belt which is devoid of seams. The endless unitary belt is (i) positioned in contact with the surface of the semiconductor wafer and (ii) capable of moving in a linear direction relative to the surface of the semiconductor wafer so as to planarize the surface of the semiconductor wafer. An associated method of linearly planarizing a surface of a semiconductor is also described.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: October 15, 2002
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Berman, Jayashree Kalpathy-Cramer
  • Patent number: 6375550
    Abstract: A chemical-mechanical polishing apparatus for polishing a first side of a semiconductor wafer includes a polishing platen having a polishing surface. The apparatus also includes a wafer carrier assembly having a carrier body. The wafer carrier assembly is adapted to (i) engage the wafer by a second side of the wafer, and (ii) apply pressure to the wafer in order to press the wafer against the polishing surface of the polishing platen. The wafer carrier assembly is operable in a first carrier configuration and a second carrier configuration. A first fixture which is configured to apply pressure to the wafer at a first number of predetermined locations is secured to the carrier body when the wafer carrier assembly is operated in the first carrier configuration.
    Type: Grant
    Filed: June 5, 2000
    Date of Patent: April 23, 2002
    Assignee: LSI Logic Corporation
    Inventor: Michael J. Berman
  • Patent number: 6347291
    Abstract: A system for precisely locating an absolute position of a target structure disposed at a known relative position on a substrate, where the substrate has devices in a pattern. Input means receive information, including a substrate size, a pattern offset, a device size, the known relative position of the target structure, and a target structure shape. Staging means receive the substrate in a known orientation. Processing means are used to locate several positions. A center position of the substrate is located from the substrate size and the known orientation of the substrate. A first intermediate position is located by combining the center position of the substrate with the pattern offset. A second intermediate position is located by combining the first intermediate position with at least a first component of the device size. A third intermediate position is located by combining the second intermediate position with the known relative position of the target structure.
    Type: Grant
    Filed: January 5, 2000
    Date of Patent: February 12, 2002
    Assignee: LSI Logic Corporation
    Inventor: Michael J. Berman
  • Patent number: 6297558
    Abstract: The present invention advantageously provides a method for filling a recess with a slurry that exhibits electrical properties similar to those of the structure which has the recess. The topological surface that includes the recess may be placed adjacent to a pad on which the slurry is disposed. The pad may be rotated to force the slurry into the recess. After the slurry is densely packed into the recess, the slurry may be cleaned from the topological surface exclusive of the recess. The slurry may be heated in order to remove the liquid portion of the slurry. The resulting topological surface is planar since a recess no longer exists therein. The technique hereof may be especially usefull for filling a recess that forms in the surface of a plug or in the surface of a fill dielectric disposed within a trench. Such recesses may form as a result of CMP or etchback.
    Type: Grant
    Filed: December 2, 1999
    Date of Patent: October 2, 2001
    Assignee: LSI Logic Corporation
    Inventor: Michael J. Berman
  • Patent number: 6273798
    Abstract: A preconditioning mechanism for preconditioning a polishing pad is described. The preconditioning mechanism includes an arm capable of being disposed over the polishing pad and a head section located on a distal end of the arm and rotatable about a central axis. Furthermore, the head section includes at least two heads oriented about the central axis and have surfaces for either conditioning or preconditioning the polishing pad, whereby rotation of the head section about the central axis by defined amounts presents at least two heads to the polishing pad so that different of the two heads can engage the polishing pad for conditioning or preconditioning depending upon how far rotation has proceeded.
    Type: Grant
    Filed: July 27, 1999
    Date of Patent: August 14, 2001
    Assignee: LSI Logic Corporation
    Inventor: Michael J. Berman
  • Patent number: 6234883
    Abstract: Provided are an apparatus and method for concurrently pad conditioning and wafer buffing on a single station of a CMP apparatus. In a preferred embodiment, the apparatus includes a two-sided conditioning/buffing device having a pad conditioner on one side and a buff pad on the other. In operation, the device is inserted between a polishing pad and a polished wafer following CMP. A differential velocity is developed between the pad conditioner and the polishing pad, for example, by contacting the pad conditioner with a rotating or orbiting polishing pad. Concurrently, the polished wafer is contacted with the buff pad on the other side of the device, and a differential velocity is developed between the two, for example, by rotating the wafer, so that the wafer is buffed.
    Type: Grant
    Filed: October 1, 1997
    Date of Patent: May 22, 2001
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Berman, Karey L. Holland
  • Patent number: 6223503
    Abstract: A method for producing hot pour product samplers that incorporates the genuine hot pour product through the use of bulk thin film application techniques such as extrusion or spray technology. The method comprises first applying a hot pour product to a base substrate, and then attaching a cover sheet by means of an adhesive or heat-seal die adhesive on either wide-web offset or narrow-web equipment.
    Type: Grant
    Filed: June 5, 2000
    Date of Patent: May 1, 2001
    Assignee: Retail Communications Corp.
    Inventors: Michael J. Berman, William Deierlein
  • Patent number: 6182420
    Abstract: A method for producing cosmetic samplers that incorporates the genuine cosmetic through the use of bulk thin film application techniques such as extrusion or spray technology. The method comprises first applying a cosmetic slurry to a base substrate and then attaching a cover sheet by means of an adhesive on either wide-web offset or label equipment.
    Type: Grant
    Filed: July 12, 1999
    Date of Patent: February 6, 2001
    Assignee: Retail Communications Corp.
    Inventors: Michael J. Berman, William Deierlein, Michael Parrotta, Phillip Cameron, Allan Cameron, III
  • Patent number: 6108093
    Abstract: An automated endpoint detection process for detecting residual metal on a surface of an integrated circuit substrate after subjecting said surface to a chemical-mechanical polishing process is described. The process includes obtaining a baseline reflected radiation signal for a surface on a standard integrated circuit substrate surface that is substantially free of residual metal, directing radiation generated from a radiation source on at least a portion of the surface of the integrated circuit substrate, detecting a resulting reflected radiation signal from the surface of the integrated circuit substrate and comparing the reflected radiation signal to the baseline reflected radiation signal and thereby determining whether residual metal is present on the surface of the integrated circuit substrate.
    Type: Grant
    Filed: June 4, 1997
    Date of Patent: August 22, 2000
    Assignee: LSI Logic Corporation
    Inventor: Michael J. Berman
  • Patent number: 6070392
    Abstract: A method for producing hot pour product samplers that incorporates the genuine hot pour product through the use of bulk thin film application techniques such as extrusion or spray technology. The method comprises first applying a hot pour product to a base substrate, and then attaching a cover sheet by means of an adhesive or heat-seal die adhesive on either wide-web offset or narrow-web equipment.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: June 6, 2000
    Assignee: Retail Communications Corp.
    Inventors: Michael J. Berman, William Deierlein
  • Patent number: 6069085
    Abstract: The present invention advantageously provides a method for filling a recess with a slurry that exhibits electrical properties similar to those of the structure which has the recess. The topological surface that includes the recess may be placed adjacent to a pad on which the slurry is disposed. The pad may be rotated to force the slurry into the recess. After the slurry is densely packed into the recess, the slurry may be cleaned from the topological surface exclusive of the recess. The slurry may be heated in order to remove the liquid portion of the slurry. The resulting topological surface is planar since a recess no longer exists therein. The technique hereof may be especially useful for filling a recess that forms in the surface of a plug or in the surface of a fill dielectric disposed within a trench. Such recesses may form as a result of CMP or etchback.
    Type: Grant
    Filed: July 23, 1997
    Date of Patent: May 30, 2000
    Assignee: LSI Logic Corporation
    Inventor: Michael J. Berman