Abstract: A dialysis machine has control circuit which detects changes in input water temperature and compensates the water heater. The control circuit detects changes in the conductivity of the dialysate concentrate and compensates the concentrate pump. Changes in supply voltage are detected and the outputs of the several sensors and the inputs to the pumps and heater comensated. The control circuit periodically calibrates the blood leak detector. In each of the feedback loops which service the heater and each of the pumps, the control circuit varies both the loop response time and the loop gain to compensate for changes in the dialysate flow rate. The resolution of the D/A converters which drive the pumps are enhanced by the control circuit by time modulating the LSB of the respective digital drive value. If any of the several sensed operating conditions varies significantly from the expected value, the control circuit terminates dialysis.

Abstract: A dialysis machine has control circuit which detects changes in input water temperature and compensates the water heater. The control circuit detects changes in the conductivity of the dialysate concentrate and compensates the concentrate pump. Changes in supply voltage are detected and the outputs of the several sensors and the inputs to the pumps and heater comensated. The control circuit periodically calibrates the blood leak detector. In each of the feedback loops which service the heater and each of the pumps, the control circuit varies both the loop response time and the loop gain to compensate for changes in the dialysate flow rate. The resolution of the D/A converters which drive the pumps are enhanced by the control circuit by time modulating the LSB of the respective digital drive value. If any of the several sensed operating conditions varies significantly from the expected value, the control circuit terminates dialysis.

Abstract: A dialysis machine has control circuit which detects changes in input water temperature and compensates the water heater. The control circuit detects changes in the conductivity of the dialysate concentrate and compensates the concentrate pump. Changes in supply voltage are detected and the outputs of the several sensors and the inputs to the pumps and heater compensated. The control circuit periodically calibrates the blood leak detector. In each of the feedback loops which service the heater and each of the pumps, the control circuit varies both the loop response time and the loop gain to compensate for changes in the dialysate flow rate. The resolution of the D/A converters which drive the pumps are enhanced by the control circuit by time modulating the LSB of the respective digital drive value. If any of the several sensed operating conditions varies significantly from the expected value, the control circuit terminates dialysis.

Abstract: A high speed processor has its speed enhanced through the use of an asynchronous operation and its arithmetic logic unit and memory circuits. The minimum possible delay time is implemented through the providing a completion pulse upon the completion of each operation and initiating a subsequent operation at the receipt of the completion pulse.

Abstract: A high speed computer system has a high speed processor for executing program sequences in a single fetch cycle; an instruction memory means for communicating with the high speed processor; a data memory for communicating with the high speed processor and a special subroutine handling operation which is implemented through a picosequencer which provides for interrupting the program, loading the contents of the instructions being implemented into a memory, executing the subroutine under the control of a picosequencer and then returning to the operation of the program.

Abstract: A high speed data processor obtains its speed through the efficient transfer of information over separate data and instruction busses, prefetching of instructions, dual working memory and architectural arrangements designed for maximum information transfer. The architecture of the data processor is such that data from any of several sources may be, either in combination or separately, channelled directly through an Arithmetic Logic Unit (ALU) so as to provide quick manipulation of the data since no extra iterations are needed in this movement. The processor uses two scratch pad or working memory areas. Both scratch pad memories communicate directly with the ALU so as to provide two operands, one from each memory and for the operation of the ALU. Two independent registers are provided which allow the linkage of computer words to obtain longer words thereby and a resulting higher precision. This linkage is accomplished by mapping and carrying the most significant bit over to the next sequentially mapped word.

Abstract: A variable function calculator utilizes a fixed program memory array such as a programmed read only memory in which a number of programs are stored depending upon the desired functions of the calculator. The calculator also includes a program counter, an instruction register, control decoders, jump-condition circuits, a clock generator, a timing generator, decoders, key input logic, a data storage array, an arithmetic logic unit, an output decoder, and a digit scanner which scans both the keyboard and display outputs. Aside from providing basic desk top calculator functions, the read only memory may be programmed so that the system provides metering functions, arithmetic teaching functions, control functions, etc. A preferred embodiment of the invention is capable of being fabricated as a monolithic integrated semiconductor system utilizing contemporary metal-insulator-semiconductor techniques.

Abstract: A variable function calculator utilizes a fixed program memory array such as a programmed read only memory in which a number of programs are stored depending upon the desired functions of the calculator. The calculator also includes a program counter, an instruction register, control decoders, jump-condition circuits, a clock generator, a timing generator, decoders, key input logic, a data storage array, an arithmetic logic unit, an output decoder, and a digit scanner which scans both the keyboard and display outputs. Aside from providing basic desk top calculator functions, the read only memory may be programmed so that the system provides metering functions, arithmetic teaching functions, control functions, etc. A preferred embodiment of the invention is capable of being fabricated as a monolithic integrated semiconductor system utilizing contemporary metal-insulator-semiconductor techniques.

Abstract: A variable function calculator utilizes a fixed program memory array such as a programmed read only memory in which a number of programs are stored depending upon the desired functions of the calculator. The calculator also includes a program counter, an instruction register, control decoders, jump-condition circuits, a clock generator, a timing generator, digit and FLAG mask decoders, key input logic, a register and FLAG data storage array, a decimal and FLAG arithmetic logic unit, an output decoder, and a digit scanner which scans both the keyboard and display outputs. Aside from providing basic desk top calculator functions, the read only memory may be programmed so that the system provides metering functions, arithmetic teaching functions, control functions, etc. A preferred embodiment of the invention is capable of being fabricated as a monolithic integrated semiconductor system utilizing contemporary metal-insulator-semiconductor techniques.

Abstract: A variable function calculator utilizes a fixed program memory array such as a programmed read only memory in which a number of programs are stored depending upon the desired functions of the calculator. The calculator also incudes a program counter, an instruction register, control decoders, jump-condition circuits, a clock generator, a timing generator, digit and FLAG mask decoders, key input logic, a register and FLAG data storage array, a decimal and FLAG arithmetic logic unit, an output decoder, and a digit scanner which scans both the keyboard and display outputs. Aside from providing basic desk top calculator functions, the read only memory may be programmed so that the system provides metering functions, arithmetic teaching functions, control functions, etc. A preferred embodiment of the invention is capable of being fabricated as a monolithic integrated semiconductor system utilizing contemporary metal insulator-semiconductor techniques.

Abstract: An electronic desk top calculator implemented in MOS/LSI technology and including a scanned keyboard input and display output. Data registers are provided in a sequentially addressed random access memory array, which is addressed by a commutator also used to generate encoded timing signals for other parts of the system and control logic. The keyboard input includes an interface register into which is entered key sense line information along with encoded timing information derived from the encoded timing signals. The contents of the interface register may be entered into the data registers or used to select an address in a program storage memory via a program counter. Bits may be read out in parallel from cells in the data registers and processed through an arithmetic logic unit and then re-entered in the same cells within a bit time or state time, so the data registers do not recirculate in the usual sense.

Abstract: An electronic phase locked loop circuit including a variable period sawtooth generator. The sawtooth generator receives digital reference clock signals and in response thereto generates sawtooth-shaped signals having the same period as said reference clock signals. A sample and hold circuit samples the sawtooth-shaped signals in response to one logical state of a sampling clock. A voltage controlled oscillator is coupled to the output of the sample and hold circuit and oscillates at a frequency proportional to the magnitude of the held sample. A feedback circuit generates the sampling clock by coupling the output of the voltage controlled oscillator to the sampling input of the sample and hold circuit.

Abstract: An electronic calculator or microprocessor system of the type preferably having keyboard input and a visual display is provided with a semiconductor chip having a memory for storing instruction words, an arithmetic unit, an instruction word decoder for controlling the arithmetic unit in response to instruction commands read out of the instruction word memory and a combined data and flag bit storage system. The combined data and flag bit storage system provides for the storage of flag bits with an associated numeric data word in a single register. Certain of the stages of the register are preferably dedicated for use as flag bit storage and certain other stages of the register are dedicated for use as numeric data storage. The arithmetic unit is preferably operable in a first mode for performing arithmetic operations in binary coded decimal format for the numeric data and in a binary format for the flag bits.

Abstract: A transceiver includes a first mixer and a detector in the receive signal path and a second mixer and modulator in the transmit signal path, all of which are coupled to and are operated by programmable counter circuits clocked by a single reference frequency generator. In one embodiment, a charge transfer device filter, which is connectable to both the receive and transmit signal paths by a switch and which has an adjustable bandwidth and center frequency, is also coupled to and operated by a programmable counter circuit which is clocked by the single reference frequency generator.

Abstract: A radio receiver receives input signals comprised of a plurality of frequency bands lying respectively within a plurality of non-overlapping frequency channels. The signals include an itermittently present reference frequency signal. The radio receiver includes an autolock circuit for measuring the frequency of the intermittently present carrier and for generating digital signals indicating its frequency. A digital processor has inputs coupled to receive the digital signals for calculating in response thereto a selectable demodulating frequency dependent upon the frequency of the intermittently present carrier.

Abstract: Disclosed is a radio system comprising mixing means for simultaneously receiving electronic input signals consisting of a plurality of non-overlapping frequency bands and first clocking signals having a first selectable frequence. The mixing means frequency shifts the input signals by the first selectable frequency. A charge transfer device transversal filter has inputs coupled to receive the frequency shifted signals. The charge transfer device filters one frequency band from the frequency shifted signals and further frequency shifts the selected band in response to a second clocking signal. Demodulator means is coupled to the output of the charge transfer device filter for demodulating the selected one further downshifted frequency band.

Abstract: A thermal printer system for actuating a plurality of groups of thermal printing elements. The system includes a first circuit in which a plurality of data words are stored, the words representing the characters to be printed. A second circuit converts the data words into printing character codes. A selected bit from each code, which bit is sequentially altered, is supplied to a third circuit for actuating the printing elements.

Abstract: A transceiver receives electronic input signals comprised of a plurality of frequency bands lying within a plurality of non-overlapping frequency channels. A mixer frequency shifts a selected band to a predetermined center frequency in response to a first clocking signal of a first selectable frequency. A charge transfer device filter is coupled to the mixer output to filter the band of the predetermined center frequency in response to a second selectable frequency clocking signal. The clocking signals are generated by clocking means which receive digital microcommands identifying the selectable frequencies. Signal level measuring means are coupled to the output of the charge transfer device filter and generate digital level signals indicating the signal level present in the filtered band. Microprocessor means are coupled to send microcommands to the clocking means for sequentially filtering various channels from the plurality, and for monitoring the resulting digital level signals.

Abstract: A programmable filter module includes a charge transfer device bandpass filter and a phase locked loop. The bandpass filter has a plurality of passbands dependent upon the frequency of a clocking signal. The phase locked loop receives a reference signal of one frequency and in response thereto, generates the clocking signals in the form N1 divided by N2 times the frequency of the reference signal, where N1 and N2 are programmable integers.

Abstract: A radio system includes a charge transfer device transversal filter for receiving electronic input signals comprised of at least one frequency band. The charge transfer device simultaneously receives a clocking signal, and filters and frequency shifts its input signals in response to the frequency of the clocking signal. Clocking means are provided for generating the clocking signal at frequencies as indicated in digital micro commands. A digital processor has outputs coupled to the clocking means for sending the micro commands to the clocking means.