Abstract: A method for fabricating a transistor having self-aligned borderless electrical contacts is disclosed. A gate stack is formed on a silicon region. An off-set spacer is formed surrounding the gate stack. A sacrificial layer that includes a carbon-based film is deposited overlying the silicon region, the gate stack, and the off-set spacer. A pattern is defined in the sacrificial layer to define a contact area for the electrical contact. The pattern exposes at least a portion of the gate stack and source/drain. A dielectric layer is deposited overlying the sacrificial layer that has been patterned and the portion of the gate stack that has been exposed. The sacrificial layer that has been patterned is selectively removed to define the contact area at the height that has been defined. The contact area for the height that has been defined is metalized to form the electrical contact.

Abstract: Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.

Abstract: Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.

Abstract: Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.

Abstract: A method for fabricating a negative thermal expanding system device includes coating a wafer with a thermally decomposable polymer, patterning the decomposable polymer into repeating disk patterns, releasing the decomposable polymer from the wafer and forming a sheet of repeating patterned disks, suspending the sheet into a first solution with seeding compounds for electroless decomposition, removing the sheet from the first solution, suspending the sheet into a second solution to electrolessly deposit a first layer material onto the sheet, removing the sheet from the second solution, suspending the sheet into a third solution to deposit a second layer of material having a lower TCE value than the first layer of material, separating the patterned disks from one another, and annealing thermally the patterned disks to decompose the decomposable polymer and creating a cavity in place of the decomposable polymer.

Abstract: A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy.

Abstract: A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy.

Abstract: A method of forming a negative coefficient of thermal expansion particle includes flattening a hollow sphere made of a first material, annealing the flattened hollow sphere at a reference temperature above a predetermined maximum use temperature to set a stress minimum of the flattened hollow sphere, and forming a coating made of a second material on the flattened hollow sphere at the reference temperature, the second material having a lower coefficient of thermal expansion than that of the first material, the negative coefficient of thermal expansion particle characterized by volumetric contraction when heated.

Abstract: A structure for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target. The structure including a first trench in a semiconductor substrate, the first trench extending from a top surface of the substrate into the substrate a first distance; an electron back-scattering layer in a bottom of the first trench; a dielectric capping layer in the trench over the back-scattering layer; and a second trench in the substrate, the second trench extending from the top surface of the substrate into the substrate a second distance, the second distance less than the first distance.

Abstract: Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.

Abstract: A pillar structure that is contacted by a vertical contact is formed in an integrated circuit. A hard mask is formed and utilized to pattern a least a portion of the pillar structure. The hard mask comprises carbon. Subsequently, the hard mask is removed. A conductive material is then deposited in a region previously occupied by the hard mask to form the vertical contact. The hard mask may, for example, comprise diamond-like carbon. The pillar structure may have a width or diameter less than about 100 nanometers.

Abstract: A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy.

Abstract: A method for fabricating a negative thermal expanding system device includes coating a wafer with a thermally decomposable polymer, patterning the decomposable polymer into repeating disk patterns, releasing the decomposable polymer from the wafer and forming a sheet of repeating patterned disks, suspending the sheet into a first solution with seeding compounds for electroless decomposition, removing the sheet from the first solution, suspending the sheet into a second solution to electrolessly deposit a first layer material onto the sheet, removing the sheet from the second solution, suspending the sheet into a third solution to deposit a second layer of material having a lower TCE value than the first layer of material, separating the patterned disks from one another, and annealing thermally the patterned disks to decompose the decomposable polymer and creating a cavity in place of the decomposable polymer.

Abstract: A method for fabricating a negative thermal expanding system device includes coating a wafer with a thermally decomposable polymer, patterning the decomposable polymer into repeating disk patterns, releasing the decomposable polymer from the wafer and forming a sheet of repeating patterned disks, suspending the sheet into a first solution with seeding compounds for electroless decomposition, removing the sheet from the first solution, suspending the sheet into a second solution to electrolessly deposit a first layer material onto the sheet, removing the sheet from the second solution, suspending the sheet into a third solution to deposit a second layer of material having a lower TCE value than the first layer of material, separating the patterned disks from one another, and annealing thermally the patterned disks to decompose the decomposable polymer and creating a cavity in place of the decomposable polymer.

Abstract: A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target including a high atomic weight layer formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.

Abstract: A method for fabricating a transistor having self-aligned borderless electrical contacts is disclosed. A gate stack is formed on a silicon region. An off-set spacer is formed surrounding the gate stack. A sacrificial layer that includes a carbon-based film is deposited overlying the silicon region, the gate stack, and the off-set spacer. A pattern is defined in the sacrificial layer to define a contact area for the electrical contact. The pattern exposes at least a portion of the gate stack and source/drain. A dielectric layer is deposited overlying the sacrificial layer that has been patterned and the portion of the gate stack that has been exposed. The sacrificial layer that has been patterned is selectively removed to define the contact area at the height that has been defined. The contact area for the height that has been defined is metalized to form the electrical contact.

Abstract: A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy.

Abstract: A method for fabricating a negative thermal expanding system device includes coating a wafer with a thermally decomposable polymer, patterning the decomposable polymer into repeating disk patterns, releasing the decomposable polymer from the wafer and forming a sheet of repeating patterned disks, suspending the sheet into a first solution with seeding compounds for electroless decomposition, removing the sheet from the first solution, suspending the sheet into a second solution to electrolessly deposit a first layer material onto the sheet, removing the sheet from the second solution, suspending the sheet into a third solution to deposit a second layer of material having a lower TCE value than the first layer of material, separating the patterned disks from one another, and annealing thermally the patterned disks to decompose the decomposable polymer and creating a cavity in place of the decomposable polymer.

Abstract: A negative coefficient of thermal expansion particle includes a first bilayer having a first bilayer inner layer and a first bilayer outer layer, and a second bilayer having a second bilayer inner layer and a second bilayer outer layer. The first and second bilayers are joined together along perimeters of the first and second bilayer outer layers and first and second bilayer inner layers, respectively. The first bilayer inner layer and the second bilayer inner layer are made of a first material and the first bilayer outer layer and the second bilayer outer layer are made of a second material. The first material has a greater coefficient of thermal expansion than that of the second material.

Abstract: A structure for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target. The structure including a first trench in a semiconductor substrate, the first trench extending from a top surface of the substrate into the substrate a first distance; an electron back-scattering layer in a bottom of the first trench; a dielectric capping layer in the trench over the back-scattering layer; and a second trench in the substrate, the second trench extending from the top surface of the substrate into the substrate a second distance, the second distance less than the first distance.