Abstract: A method for forming an integrated circuit assembly comprises forming first solder bumps on a first die, and forming a first structure comprising the first die, the first solder bumps, a first flux, and a first substratum. The first die is placed upon the first substratum. The first solder bumps are between the first die and the first substratum. The first flux holds the first die substantially flat and onto the first substratum.

Abstract: A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.

Abstract: A method and apparatus for speculatively executing a single threaded program within a multi-core processor which includes identifying an idle core within the multi-core processor, performing a look ahead operation on the single thread instructions to identify speculative instructions within the single thread instructions, and allocating the idle core to execute the speculative instructions.

Abstract: A method and apparatus for speculatively executing a single threaded program within a multi-core processor which includes identifying an idle core within the multi-core processor, performing a look ahead operation on the single thread instructions to identify speculative instructions within the single thread instructions, and allocating the idle core to execute the speculative instructions.

Abstract: Secure communication of data between devices includes encrypting unencrypted data at a first device by reordering unencrypted bits provided in parallel on a device bus, including data and control bits, from an unencrypted order to form encrypted data including a plurality of encrypted bits in parallel in an encrypted order defined by a key. The encrypted data may be transmitted to another device where the encrypted data is decrypted by using the key to order the encrypted bits to restore the unencrypted order thereby to reform the unencrypted data.

Abstract: A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.

Abstract: A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.

Abstract: A method for optimizing execution of a single threaded program on a multi-core processor. The method includes dividing the single threaded program into a plurality of discretely executable components while compiling the single threaded program; identifying at least some of the plurality of discretely executable components for execution by an idle core within the multi-core processor; and enabling execution of the at least one of the plurality of discretely executable components on the idle core.

Abstract: A design structure for a processor may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may control heat generation in a multi-core processor. The design structure may specify that each processor core includes a temperature sensor that reports temperature information to a processor controller. The design structure may also specify that if a particular processor core exceeds a predetermined temperature, the processor controller disables that processor core to allow that processor core to cool. The design structure may also specify that the processor controller enables the previously disabled processor core when the previously disabled processor core cools sufficiently to a normal operating temperature. In this manner, a multi-core processor may avoid undesirable hot spots that impact processor life.

Abstract: According to one aspect of the present disclosure a method and technique for managing data transfer is disclosed. The method includes comparing, by a processor unit of a data processing system, data to be written to a memory subsystem to a stored data pattern and, responsive to determining that the data matches the stored data pattern, replacing the matching data with a pattern tag corresponding to the matching data pattern. The method also includes transmitting the pattern tag to the memory subsystem.

Abstract: A multiprocessor system which includes automatic workload distribution. As threads execute in the multiprocessor system, an operating system or hypervisor continuously learns the execution characteristics of the threads and saves the information in thread-specific control blocks. The execution characteristics are used to generate thread performance data. As the thread executes, the operating system continuously uses the performance data to steer the thread to a core that will execute the workload most efficiently.

Abstract: A method for automatically initializing the operational settings of a system from information stored within a non-volatile storage of an integrated circuit so that the operational requirements of the integrated circuit, which may be a microprocessor, are met by the system when the system is operating. During manufacturing test, environmental requirements of the integrated circuit are determined and stored within the non-volatile storage of the integrated circuit. During system initialization, environmental control values such as required operating voltage and frequency and cooling requirements are determined from the test values, which are read from the integrated circuit. The values are read by an interface of the system from an interface of the integrated circuit. System settings are controlled by the values to provide the required operating environment and the values may be captured within the system for subsequent operations and initialization sequences.

Abstract: Methods and apparatus for forming an integrated circuit assembly are presented, for example, three dimensional integrated circuit assemblies. Lower height 3DIC assemblies due Use of, for example, thinned wafers, low-height solder bumps, and through silicon vias provide for low height three dimensional integrated circuit assemblies. For example, a method for forming an integrated circuit assembly comprises forming first solder bumps on a first die, and forming a first structure comprising the first die, the first solder bumps, a first flux, and a first substratum. The first die is placed upon the first substratum. The first solder bumps are between the first die and the first substratum. The first flux holds the first die substantially flat and onto the first substratum.

Abstract: A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.

Abstract: A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.

Abstract: The disclosed methodology and apparatus may reduce heat generation in a multi-core processor. In one embodiment, a multi-core processor cycles selected processor cores off in a predetermined pattern across the processor die over time to reduce the average heat generation by the processor. The disclosed multi-core processor may reduce or avoid undesirable hot spots that impact processor life.

Abstract: The disclosed methodology and apparatus may control heat generation in a multi-core processor. In one embodiment, each processor core includes a temperature sensor that reports temperature information to a processor controller. If a particular processor core exceeds a predetermined temperature, the processor core disables that processor core to allow it to cool. The processor core enables the previously disabled processor when the previously disabled processor core cools sufficiently to a normal operating temperature. The disclosed multi-core processor may avoid undesirable hot spots that impact processor life.

Abstract: A method and apparatus for speculatively executing a single threaded program within a multi-core processor which includes identifying an idle core within the multi-core processor, performing a look ahead operation on the single thread instructions to identify speculative instructions within the single thread instructions, and allocating the idle core to execute the speculative instructions.

Abstract: A method for optimizing execution of a single threaded program on a multi-core processor. The method includes dividing the single threaded program into a plurality of discretely executable components while compiling the single threaded program; identifying at least some of the plurality of discretely executable components for execution by an idle core within the multi-core processor; and enabling execution of the at least one of the plurality of discretely executable components on the idle core.

Abstract: A method and apparatus for speculatively executing a single threaded program within a multi-core processor which includes identifying an idle core within the multi-core processor, performing a look ahead operation on the single thread instructions to identify speculative instructions within the single thread instructions, and allocating the idle core to execute the speculative instructions.