Patents by Inventor Michael Jay Shapiro

Michael Jay Shapiro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090164759
    Abstract: A method and apparatus for speculatively executing a single threaded program within a multi-core processor which includes identifying an idle core within the multi-core processor, performing a look ahead operation on the single thread instructions to identify speculative instructions within the single thread instructions, and allocating the idle core to execute the speculative instructions.
    Type: Application
    Filed: December 19, 2007
    Publication date: June 25, 2009
    Inventors: Robert H. Bell, JR., Louis Bennie Capps, JR., Michael A. Paolini, Michael Jay Shapiro
  • Publication number: 20090094446
    Abstract: A method for automatically initializing the operational settings of a system from information stored within a non-volatile storage of an integrated circuit so that the operational requirements of the integrated circuit, which may be a microprocessor, are met by the system when the system is operating. During manufacturing test environmental requirements of the integrated circuit are determined and stored within the non-volatile storage of the integrated circuit. During system initialization, environmental control values such as required operating voltage and frequency and cooling requirements are determined from the test values, which are read from the integrated circuit. The values are read by an interface of the system from an interface of the integrated circuit. System settings are controlled by the values to provide the required operating environment and the values may be captured within the system for subsequent operations and initialization sequences.
    Type: Application
    Filed: November 25, 2008
    Publication date: April 9, 2009
    Inventors: Louis Bennie Capps, JR., Mark Elliott Hack, Steven Paul Hartman, Michael Jay Shapiro
  • Patent number: 7472297
    Abstract: A method for automatically initializing the operational settings of a system from information stored within a non-volatile storage of an integrated circuit so that the operational requirements of the integrated circuit, which may be a microprocessor, are met by the system when the system is operating. During manufacturing test, environmental requirements of the integrated circuit are determined and stored within the non-volatile storage of the integrated circuit. During system initialization, environmental control values such as required operating voltage and frequency and cooling requirements are determined from the test values, which are read from the integrated circuit. The values are read by an interface of the system from an interface of the integrated circuit. System settings are controlled by the values to provide the required operating environment and the values may be captured within the system for subsequent operations and initialization sequences.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: December 30, 2008
    Assignee: International Business Machines Corporation
    Inventors: Louis Bennie Capps, Jr., Mark Elliott Hack, Steven Paul Hartman, Michael Jay Shapiro
  • Publication number: 20080234955
    Abstract: A computer implemented method, data processing system, and computer usable code are provided for burn-in testing of a multiprocessor. A process identifies a power management data set for a plurality of processor cores associated with the multiprocessor. The process selects one or more of the plurality of processor cores to form a selected set of processor cores based upon the power management data set. The process initiates a burn-in test across the selected set of processor cores. In response to a determination that all processor cores in the plurality of processor cores have not been selected, the process repeats the above selecting and initiating steps until all the processor cores have been selected.
    Type: Application
    Filed: May 2, 2008
    Publication date: September 25, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis Bennie Capps, Anand Haridass, Ronald Edward Newhart, Michael Jay Shapiro
  • Patent number: 7389195
    Abstract: A computer implemented method, data processing system, and computer usable code are provided for burn-in testing of a multiprocessor. A process identifies a power management data set for a plurality of processor cores associated with the multiprocessor. The process selects one or more of the plurality of processor cores to form a selected set of processor cores based upon the power management data set. The process initiates a burn-in test across the selected set of processor cores. In response to a determination that all processor cores in the plurality of processor cores have not been selected, the process repeats the above selecting and initiating steps until all the processor cores have been selected.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: June 17, 2008
    Assignee: International Business Machines Corporation
    Inventors: Louis Bennie Capps, Jr., Anand Haridass, Ronald Edward Newhart, Michael Jay Shapiro
  • Publication number: 20080052542
    Abstract: A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.
    Type: Application
    Filed: August 24, 2006
    Publication date: February 28, 2008
    Inventors: Louis Bennie Capps, Warren D. Dyckman, Joanne Ferris, Anand Haridass, James Douglas Jordan, Ronald Edward Newhart, Michael Richard Ouellette, Michael Jay Shapiro
  • Publication number: 20080028236
    Abstract: The disclosed methodology and apparatus may reduce heat generation in a multi-core processor. In one embodiment, a multi-core processor cycles selected processor cores off in a predetermined pattern across the processor die over time to reduce the average heat generation by the processor. The disclosed multi-core processor may reduce or avoid undesirable hot spots that impact processor life.
    Type: Application
    Filed: July 26, 2006
    Publication date: January 31, 2008
    Applicant: IBM Corporation
    Inventors: Louis Bennie Capps, Warren D. Dyckman, Michael Jay Shapiro
  • Publication number: 20080028244
    Abstract: The disclosed methodology and apparatus may control heat generation in a multi-core processor. In one embodiment, each processor core includes a temperature sensor that reports temperature information to a processor controller. If a particular processor core exceeds a predetermined temperature, the processor core disables that processor core to allow it to cool. The processor core enables the previously disabled processor when the previously disabled processor core cools sufficiently to a normal operating temperature. The disclosed multi-core processor may avoid undesirable hot spots that impact processor life.
    Type: Application
    Filed: July 26, 2006
    Publication date: January 31, 2008
    Applicant: IBM Corporation
    Inventors: Louis Bennie Capps, Warren D. Dyckman, Michael Jay Shapiro
  • Patent number: 6268660
    Abstract: A package for integrated circuit chips. The package contains a silicon substrate having a top surface and a bottom surface. The package also contains a first means for electrically connecting the integrated circuits to the substrate attached to the top surface of the substrate. A multilevel wiring is located at the top surface and is coupled to the first connecting means and serves as a communication link among a plurality of the first connecting means to enable multi-chip processing. A via containing means for coupling the multilevel wiring at the top surface to the bottom surface runs through the substrate from the bottom surface to the top surface. A second means is also present for connecting the coupling means at the bottom surface of the substrate with external components.
    Type: Grant
    Filed: March 5, 1999
    Date of Patent: July 31, 2001
    Assignee: International Business Machines Corporation
    Inventors: Sang Hoo Dhong, Harm Peter Hofstee, Michael Jay Shapiro
  • Patent number: 6221769
    Abstract: A method for providing a through wafer connection to an integrated circuit silicon package. A hole is first created in the silicon package with an inner surface area extending from the bottom surface of the silicon package to the top surface of the silicon package. The hole is created by one of two methods. The first involves mechanical drilling with a diamond bit rotated at a high rate of speed. The second involves ultrasonically milling utilizing a slurry and steel fingers. The inner surface area of the hole is covered with an insulating material to insulate the conductive material which is later deposited and to serve as a diffusion barrier, then a seed material is placed in the hole. Finally, the hole is filled with a conductive material which is utilized to provide large power inputs or signaling connections to the integrated circuit chips.
    Type: Grant
    Filed: March 5, 1999
    Date of Patent: April 24, 2001
    Assignee: International Business Machines Corporation
    Inventors: Sang Hoo Dhong, Kevin John Nowka, Michael Jay Shapiro
  • Patent number: 6166437
    Abstract: A silicon wafer is etched to form a first and second series of guidance features. The features of the first series are larger than and surround the features of the second series. The second series is clustered into groups and a hole is formed in the center of each group. The wafer is designed to integrate a silicon package having preformed contacts with a plurality of silicon-based chips. The package and each chip has a series of guidance recesses which correspond to the guidance features of the first and second series, respectively. One chip is placed on top of each group of the second series, and the package is placed on top of the first series. The recesses in the package and chips will precisely align with and slidingly engage the upper ends of the features. Since the features of the first series are larger than those of the second series, there is a clearance between the package and the chips.
    Type: Grant
    Filed: April 12, 1999
    Date of Patent: December 26, 2000
    Assignee: International Business Machines Corporation
    Inventors: Sang Hoo Dhong, Kevin John Nowka, Michael Jay Shapiro
  • Patent number: 5712702
    Abstract: A marker element is included in a deposition chamber. After use of the chamber to deposit films or coatings on workpieces, the chamber is cleaned to remove materials which may contaminate future processing of workpieces in the chamber. The composition of the gas exhausted from the chamber during the cleaning process is monitored, and a characteristic of the marker element is sensed. The cleaning gas is terminated in response to the sensed characteristic of the marker element having a predetermined value, such as a peak intensity or the return to a baseline value after peaking. The present invention effectively solves the problem of overcleaning or undercleaning the chamber based upon an estimated film thickness build up.
    Type: Grant
    Filed: December 6, 1996
    Date of Patent: January 27, 1998
    Assignee: International Business Machines Corporation
    Inventors: Vincent James McGahay, James Gardner Ryan, Michael Jay Shapiro, Christopher Joseph Waskiewicz