Abstract: A display controller includes a data bus interface which transfers data to the display controller from external sources. A modulation data register coupled to the data bus interface receives a first quantity of modulation data through the data bus interface. A decoder coupled to the modulation data register receives the first quantity of modulation data and decodes graphics data according to the first quantity of modulation data in order to generate display data. A modulation data address counter counts quantities of modulation data that are transferred through the data bus interface and generates a load modulation data signal when a preprogrammed total quantity of modulation data has been transferred through the data bus interface. A method used by a display controller of accessing modulation data from an external memory is also disclosed.

Abstract: A clock generation circuit for a display controller includes an intermediate dot clock generation circuit which receives an input clock signal and in response thereto generates an intermediate dot clock signal having a plurality of dot clock pulses. A row pulse generation circuit is coupled to the intermediate dot clock generation circuit and counts the intermediate dot clock signal dot clock pulses and generates a row pulse after a predetermined number of dot clock pulses and a programmable offset time. The row pulse generation circuit also generates a final dot clock signal by masking the intermediate dot clock signal with the programmable offset time after the predetermined number of dot clock pulses. A method of adjusting a rate at which data is transferred to a display screen is also disclosed.

Abstract: A power management system is disclosed. The system includes an oscillator interface for use in a power management system, a power recycle circuit for use in a power management system, a pad clock and self test for use in a power management system, a clock enable circuit for use in a power management system, a power level detect circuit for use in a power management system, an internal source clock generation circuit for use in a power management system, and a power-save mode change detection circuit for use in a power management system. The oscillator interface includes an interface circuit for interfacing with an external oscillator used as a source of oscillations. A clock stabilization filter masks out spurious crystal frequencies in the oscillations during start-up of the power management system following an enabling of a feedback loop. The clock stabilization filter has circuitry which provides that the oscillations will start with a rising transition after filtering.

Abstract: An input/output buffer including a bidirectional node, an output stage, an input stage, and a control circuit. The output stage has a first n-channel transistor coupled between the bidirectional node and a voltage supply node for pulling-up the bidirectional node, and first and second p-channel transistors coupled between the bidirectional node and the voltage supply node for pulling-up the bidirectional node. The input stage has a first inverter stage coupled between the bidirectional node and a first intermediate node and a second inverter stage coupled between the bidirectional node and a second intermediate node. The input stage also has a second n-channel transistor coupled between the first intermediate node and a ground node and a third n-channel transistor coupled between the second intermediate node and the ground node. The control circuit is coupled to the output stage and to the input stage and enables the output stage when in an output mode and disables the output stage when in an input mode.