Abstract: The disclosure provides a nozzle adapted for placement within a flowpath of a turbomachine. The nozzle includes an airfoil having a suction side; a pressure side opposing the suction side; a leading edge between the pressure side and the suction side; a trailing edge opposing the leading edge and between the pressure side and the suction side; a root region at a first radial end; a tip region at a second radial end opposite the first radial end; and a midspan region between the root region and the tip region. An endwall is connected with the root region or the tip region of the airfoil along the suction side, the pressure side, the trailing edge, and the leading edge. The trailing edge of the airfoil has an elliptical shape having a nominal profile substantially in accordance with Cartesian coordinate values of X, Y, and Z set forth in TABLE I.

Abstract: A cockpit center console armrest includes a base member configured for mounting to a floor, an extending member mechanically coupled to the base member, and an armrest mechanically coupled to the extending member. The extending member includes an inner telescoping member configured for sliding within an outer telescoping member for adjusting a height of the armrest. A lever exposed on an underside of the armrest is configured for actuating a release mechanism. The release mechanism is configured for releasably securing the inner telescoping member to the outer telescoping member. A pivot axis pivotably couples the extending member to the base member such that the extending member is rotatable for rotating the armrest between a deployed orientation and a retracted orientation.

Abstract: Data processing apparatuses and methods of data processing are disclosed wherein a processing element maintains a buffer in the memory in support of the data processing it performs. A write pointer indicates a current write location in the buffer. A cache holds copies of the data which are subject to the data processing operations and allocations into the cache from the memory and write-backs from the cache to the memory are performed in cache line units of data. When the processing element performs a data write to the buffer at a location determined by the write pointer, the processor updates the write pointer in an update direction corresponding to a progression direction of data writes in the buffer, and further locations in the progression direction in the buffer between the location indicated by the write pointer and a boundary location are signalled to be written with a predetermined value.

Abstract: A data processing apparatus and method having processing circuitry, and trace circuitry having a trace buffer; write pointer storage, and a call depth counter, wherein the trace circuitry generates trace data processing first event activities: modify the call depth counter in a first direction, store first trace data indicative of the first event, and modify the write pointer to point to a next location in the trace buffer; in response to a second event, when the call depth counter is not equal to a threshold call depth, to: modify the call depth counter direction and the write pointer to point to a previous location in the trace buffer; and in response to the second event, when the call depth counter is equal to the threshold call depth, to store second trace data indicative of the second event in the trace buffer at the current location.

Abstract: A technique for collecting state information of an apparatus comprising a processing pipeline for executing a sequence of instructions, and interesting instruction designation circuitry for identifying at least one of the instructions in the sequence as being an interesting instruction. Each interesting instruction is an instruction for which given state information of the apparatus associated with execution of that interesting instruction is to be collected. The interesting instruction designation circuitry is arranged, for each identified interesting instruction, to apply defined selection criteria to determine a further instruction later in the sequence of instructions than the interesting instruction, and to mark that further instruction as having a synchronous exception associated therewith. The processing pipeline is responsive to the further instruction, which causes the processing pipeline to execute a given exception handling routine in order to collect the given state information.

Abstract: A non-linear dynamic process such as multiphase flow is characterized to determine a condition of the process. A sensor may obtain information about strain, vibration, flow rate, etc. during the process. That sensor data may be plotted, and at least one perceptual hash can be generated from the plot. The perceptual hash can be compared against a database storing plots or hashes for non-linear dynamic responses for different sensor types or processes. A best fit hash may be identified and used to determine what conditions are occurring in the field, or multiple near fits can define an envelope of experimental/reference conditions with similar non-linear dynamics to the field system. Multiple hash comparisons may be used to refine the envelope, determine a best fit, or determine what measurement would help discriminate the flow conditions.

Abstract: Processing circuitry performs data processing operations in response to instructions fetched from a cache or memory or micro-operations decoded from the instructions. Sampling circuitry selects a subset of instructions or micro-operations as sampled operations to be profiled. Profiling circuitry captures, in response to processing of an instruction or micro-operation selected as a sampled operation, a sample record specifying an operation type of the sampled operation and information about behaviour of the sampled operation which is directly attributed to the sampled operation. The profiling circuitry can include, in the sample record for a sampled operation corresponding to a given instruction, a reference instruction address indicator indicative of an address of a reference instruction appearing earlier or later in program order than the given instruction, for which control flow is sequential between any instructions occurring between the reference instruction and the given instruction in program order.

Abstract: An apparatus and method are provided for generating and processing a trace stream indicative of instruction execution by processing circuitry. An apparatus has an input interface for receiving instruction execution information from the processing circuitry indicative of a sequence of instructions executed by the processing circuitry, and trace generation circuitry for generating from the instruction execution information a trace stream comprising a plurality of trace elements indicative of execution by the processing circuitry of instruction flow changing instructions within the sequence.

Abstract: Apparatus for data processing and a method of data processing are provided. Data processing operations are performed in response to data processing instructions. An error exception condition is set if a data processing operation has not been successful. It is determined if an error memory barrier condition exists and an error memory barrier procedure is performed in dependence on whether the error memory barrier condition exists. The error memory barrier procedure comprises, if the error exception condition is set and if an error mask condition is set: setting a deferred error exception condition and clearing the error exception condition.

Abstract: To access metadata when debugging a device, debug access port circuitry including a debug interface receives commands from a debugger, and a bus interface coupled to a bus enables the debugger to access a memory system of the device. The device operates on data granules having associated metadata items, and the bus interface enables communication of both the data granules and the metadata items over the bus. The debug access port circuitry has storage elements accessible via the commands issued from the debugger, such that the accesses performed within the memory system via the bus interface are controlled in dependence on the storage elements accessed by the commands. A metadata storage element stores metadata items, and the debug access port circuitry is responsive to a command from the debugger to perform a memory direct access to transfer metadata items between the metadata storage element and the memory system.

Abstract: Data processing apparatus comprises vector processing circuitry to selectively apply vector processing operations defined by vector processing instructions to generate one or more data elements of a data vector comprising a plurality of data elements at respective data element positions of the data vector, according to the state of respective predicate flags associated with the positions of the data vector; and generator circuitry to generate instruction sample data indicative of processing activities of the vector processing circuitry for selected ones of the vector processing instructions, instruction sample data indicating at least the state of the predicate flags at execution of the selected vector processing instructions.

Abstract: A method of characterizing a subterranean geologic formation's response to hydraulic fracturing is presented.

Abstract: An apparatus and method are provided to control assertion of a trigger signal to processing circuitry. The apparatus has evaluation circuitry to receive program instruction execution information indicative of a program instruction executed by the processing circuitry, which is arranged to perform an evaluation operation to determine with reference to evaluation information whether the program instruction execution information indicates presence of a trigger condition. Trigger signal generation circuitry is used to assert a trigger signal to the processing circuitry in dependence on whether the trigger condition is determined to be present. Further, filter circuitry is arranged to receive event information indicative of at least one event occurring within the processing circuitry, and is arranged to determine with reference to filter control information and that event information whether a qualifying condition is present.

Abstract: A data processing apparatus is provided that includes monitor circuitry to produce local trace data indicating behaviour of the data processing apparatus. Interface circuitry communicates with a second data processing apparatus and encoding circuitry produces an encoded instruction to cause the local trace data to be stored in storage circuitry of the second data processing apparatus or to be output at output circuitry of the second data processing apparatus. The interface circuitry transmits the encoded instruction to the second data processing apparatus.

Abstract: An apparatus for generating a virtual reality environment comprising: controller circuitry configured to: insert a captured image of an object in the virtual reality environment; move the captured image within the virtual reality environment; pause the movement of the captured image in the virtual reality environment; generate a rendered representation of at least part of the captured image; replace the at least part of the captured image with the rendered representation in the virtual reality environment; and move the rendered representation within the virtual reality environment.

Abstract: In an apparatus performing multi-threaded data processing event handling circuitry receives event information from the data processing circuitry indicative of an event which has occurred during the data processing operations. Visibility configuration storage holds a set of visibility configuration values, each visibility configuration value associated with a thread of the multiple threads and the event handling circuitry adapts its use of the event information to restrict visibility of the event information for software of threads other than the thread which generated the event information when a visibility configuration value for the thread which generated the event information has a predetermined value. This allows multi-threaded event monitoring to be supported, whilst protecting event information from a particular thread for which it is desired to limit its visibility to software of other threads.

Abstract: A technique is provided for accessing metadata when debugging a program to be executed on processing circuitry. The processing circuitry operates on data formed of data granules having associated metadata items. A method of operating a debugger is provided that comprises controlling the performance of metadata access operations when the debugger decides to access a specified number of metadata items. In particular, the specified number is such that the metadata access operation needs to be performed by the processing circuitry multiple times in order to access the specified number of metadata items. Upon deciding to access a specified number of metadata items, the debugger issues at least one command to cause the processing circuitry to perform a plurality of instances of the metadata access operation in order to access at least a subset of the specified number of metadata items.

Abstract: An apparatus for generating a trace stream, a method for generating a trace stream, an apparatus for receiving a trace stream and a method of receiving a trace stream are provided. Header items and payload items in the trace stream are respectively grouped together into a contiguous sequence of header items and a contiguous sequence of payload items. This can for example facilitate the production of a trace stream in which the trace stream is aligned to a predetermined length (e.g. corresponding to an alignment of a memory in which the trace stream is to be stored) thus facilitating its interpretation.

Abstract: An apparatus for generating a graphical representation of a content display in a virtual reality environment, comprising: controller circuitry configured to determine a position of a device relative to a virtual reality headset in the real world, and when the device is at a predetermined position in front of the virtual reality headset, the controller circuitry is further configured to: generate a graphical representation of a content display in the virtual reality environment, the position of the graphical representation in the virtual reality environment being determined by the real world position of the device in front of the virtual reality headset, wherein the size of the graphical representation of a content display is changed in dependence on the position of the distance between the virtual reality headset and the device, wherein, in response to a user input, the controller circuitry is configured to: lock the position of the graphical representation of the content display in the virtual reality enviro

Abstract: An image processing method includes partitioning an image under test to form a plurality of contiguous image segments having similar image properties, deriving feature data from a subset including one or more of the image segments, and comparing the feature data from the subset of image segments with feature data derived from respective image segments of one or more other images so as to detect a similarity between the image under test and the one or more other images.