Patents by Inventor Michael John Williams

Michael John Williams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210309514
    Abstract: A solid state storage system includes a pressure-sealed storage unit defining an interior and having an outlet, an upper manifold and a lower manifold separated by a dividing plane having a set of ports, a set of chambers, and a solid state storage, wherein at least some gas is supplied to the outlet.
    Type: Application
    Filed: June 21, 2021
    Publication date: October 7, 2021
    Inventors: Colin John HALSEY, Michael David BAILEY, Ross Jonathan WILLIAMS
  • Patent number: 11138794
    Abstract: An apparatus for generating a virtual reality environment comprising: controller circuitry configured to: insert a captured image of an object in the virtual reality environment; move the captured image within the virtual reality environment; pause the movement of the captured image in the virtual reality environment; generate a rendered representation of at least part of the captured image; replace the at least part of the captured image with the rendered representation in the virtual reality environment; and move the rendered representation within the virtual reality environment.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: October 5, 2021
    Assignee: Sony Corporation
    Inventors: Michael John Williams, Paul Edward Prayle, Michael Goldman, William Jack Leathers-Smith
  • Publication number: 20210273451
    Abstract: A power restoration system for restoring power to feeder segments in response to a fault. The system includes a reclosing device having a switch and one or more sensors for measuring current and/or voltage on the feeder, where the reclosing device performs a pulse testing process to determine circuit fault conditions. The system also includes a plurality of switching devices electrically coupled along the feeder, where each switching device includes a section switch and one or more sensors for measuring current and/or voltage on the at least one feeder. In one embodiment, each switching device recognizes predetermined pulse codes having a sequence of pulses, where the reclosing device uses the pulse testing process to generate and selectively transmit defined pulse codes on the feeder that selectively cause the section switches to change states between an open state and a closed state depending on the code.
    Type: Application
    Filed: February 25, 2021
    Publication date: September 2, 2021
    Applicant: S&C Electric Company
    Inventors: Martin T. Bishop, Stephen E. Williams, Michael John Meisinger, SR.
  • Patent number: 11080106
    Abstract: In an apparatus performing multi-threaded data processing event handling circuitry receives event information from the data processing circuitry indicative of an event which has occurred during the data processing operations. Visibility configuration storage holds a set of visibility configuration values, each visibility configuration value associated with a thread of the multiple threads and the event handling circuitry adapts its use of the event information to restrict visibility of the event information for software of threads other than the thread which generated the event information when a visibility configuration value for the thread which generated the event information has a predetermined value. This allows multi-threaded event monitoring to be supported, whilst protecting event information from a particular thread for which it is desired to limit its visibility to software of other threads.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: August 3, 2021
    Assignee: ARM Limited
    Inventors: Michael John Williams, Simon John Craske
  • Patent number: 11048617
    Abstract: A technique is provided for accessing metadata when debugging a program to be executed on processing circuitry. The processing circuitry operates on data formed of data granules having associated metadata items. A method of operating a debugger is provided that comprises controlling the performance of metadata access operations when the debugger decides to access a specified number of metadata items. In particular, the specified number is such that the metadata access operation needs to be performed by the processing circuitry multiple times in order to access the specified number of metadata items. Upon deciding to access a specified number of metadata items, the debugger issues at least one command to cause the processing circuitry to perform a plurality of instances of the metadata access operation in order to access at least a subset of the specified number of metadata items.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: June 29, 2021
    Assignee: Arm Limited
    Inventors: Michael John Williams, Graeme Peter Barnes, John Michael Horley
  • Patent number: 11036616
    Abstract: An apparatus for generating a trace stream, a method for generating a trace stream, an apparatus for receiving a trace stream and a method of receiving a trace stream are provided. Header items and payload items in the trace stream are respectively grouped together into a contiguous sequence of header items and a contiguous sequence of payload items. This can for example facilitate the production of a trace stream in which the trace stream is aligned to a predetermined length (e.g. corresponding to an alignment of a memory in which the trace stream is to be stored) thus facilitating its interpretation.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: June 15, 2021
    Assignee: ARM LIMITED
    Inventors: Michael John Williams, John Michael Horley
  • Patent number: 11003256
    Abstract: An apparatus for generating a graphical representation of a content display in a virtual reality environment, comprising: controller circuitry configured to determine a position of a device relative to a virtual reality headset in the real world, and when the device is at a predetermined position in front of the virtual reality headset, the controller circuitry is further configured to: generate a graphical representation of a content display in the virtual reality environment, the position of the graphical representation in the virtual reality environment being determined by the real world position of the device in front of the virtual reality headset, wherein the size of the graphical representation of a content display is changed in dependence on the position of the distance between the virtual reality headset and the device, wherein, in response to a user input, the controller circuitry is configured to: lock the position of the graphical representation of the content display in the virtual reality enviro
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: May 11, 2021
    Assignee: Sony Corporation
    Inventors: Michael John Williams, Paul Edward Prayle, Michael Goldman, William Jack Leathers-Smith
  • Patent number: 11004129
    Abstract: An image processing method includes partitioning an image under test to form a plurality of contiguous image segments having similar image properties, deriving feature data from a subset including one or more of the image segments, and comparing the feature data from the subset of image segments with feature data derived from respective image segments of one or more other images so as to detect a similarity between the image under test and the one or more other images.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: May 11, 2021
    Assignee: Sony Europe B.V.
    Inventors: Mikael Carl Lang, Robert Mark Stefan Porter, Paul Edward Prayle, Ratna Beresford, Jonathan Richard Thorpe, Michael John Williams
  • Publication number: 20210034362
    Abstract: Data processing apparatus comprises vector processing circuitry to selectively apply vector processing operations defined by vector processing instructions to generate one or more data elements of a data vector comprising a plurality of data elements at respective data element positions of the data vector, according to the state of respective predicate flags associated with the positions of the data vector; and generator circuitry to generate instruction sample data indicative of processing activities of the vector processing circuitry for selected ones of the vector processing instructions, instruction sample data indicating at least the state of the predicate flags at execution of the selected vector processing instructions.
    Type: Application
    Filed: February 15, 2019
    Publication date: February 4, 2021
    Inventors: Michael John WILLIAMS, Nigel John STEPHENS
  • Publication number: 20210034503
    Abstract: A technique is provided for accessing metadata when debugging a program to be executed on processing circuitry. The processing circuitry operates on data formed of data granules having associated metadata items. A method of operating a debugger is provided that comprises controlling the performance of metadata access operations when the debugger decides to access a specified number of metadata items. In particular, the specified number is such that the metadata access operation needs to be performed by the processing circuitry multiple times in order to access the specified number of metadata items. Upon deciding to access a specified number of metadata items, the debugger issues at least one command to cause the processing circuitry to perform a plurality of instances of the metadata access operation in order to access at least a subset of the specified number of metadata items.
    Type: Application
    Filed: January 17, 2019
    Publication date: February 4, 2021
    Inventors: Michael John WILLIAMS, Graeme Peter BARNES, John Michael HORLEY
  • Publication number: 20200394119
    Abstract: An apparatus and method are provided for accessing metadata when debugging a device. In particular, debug access port circuitry is provided that comprises a debug interface to receive commands from a debugger, and a bus interface to couple to a bus to enable the debugger to access a memory system of the device. The device operates on data formed of data granules having associated metadata items, and the bus interface enables communication of both the data granules and the metadata items over the bus between the memory system and the bus interface. The debug access port circuitry further has a plurality of storage elements accessible via the commands issued from the debugger, such that the accesses performed within the memory system via the bus interface are controlled in dependence on the storage elements accessed by the commands.
    Type: Application
    Filed: January 17, 2019
    Publication date: December 17, 2020
    Inventors: Michael John WILLIAMS, John Michael HORLEY
  • Patent number: 10776120
    Abstract: There is provided an apparatus comprising processing circuitry to execute a transaction comprising a number of program instructions that execute to generate updates to state data, to commit the updates if the transaction completes without a conflict, and to generate trace control signals during execution of the number of program instructions. The processing circuitry uses at least one resource during execution of the program instructions. Transaction trace circuitry generates trace items in response to the trace control signals. In response to the trace control signals indicating that a change in a usage level of the at least one resource has occurred during execution of the program instructions, the transaction trace circuitry generates at least one trace item that indicates the usage level of the at least one resource.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: September 15, 2020
    Assignee: ARM Limited
    Inventors: Michael John Williams, John Michael Horley, Stephan Diestelhorst, Richard Roy Grisenthwaite
  • Patent number: 10747647
    Abstract: A method, apparatus and system are provided for diagnosing a processor executing a stream of instructions by causing the processor to execute the stream of instructions in a sequence of stages with a diagnostic exception being taken between each stage. The method involves controlling the processor in a current stage, when a point is reached where the diagnostic exception is to be taken, to store in a storage location type indicator information comprising a type indicator for a current instruction in the stream and a type indicator for a next instruction in the stream. The diagnostic exception is then taken, causing a diagnostic operation to be performed which includes accessing the type indicator information from the storage location and, dependent on the type indicator for the current instruction and the type indicator for the next instruction, determining control information to identify at least one trigger condition for a next diagnostic exception.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: August 18, 2020
    Assignee: ARM Limited
    Inventors: Damien Robin Martin, Clément Marc Demongeot, Michael John Williams
  • Patent number: 10719383
    Abstract: A data processing system (2) supports non-speculative execution of vector load instructions that perform at least one contingent load of a data value. Fault detection circuitry (26) serves to detect whether a contingent load is fault-generating contingent load or a fault-free contingent load. Contingent load suppression circuitry (28) detects and suppresses a fault-free contingent load that matches a predetermined criteria that may result in an undesired change of architectural state (undesired side-effect). Examples of such predetermined criteria are that the contingent load is to a non-memory device or that the contingent load will trigger a diagnostic response such as entry of a halting debug halting mode or triggering of a debug exception.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: July 21, 2020
    Assignee: ARM Limited
    Inventors: Nigel John Stephens, Michael John Williams, Richard Roy Grisenthwaite
  • Patent number: 10718877
    Abstract: A method of analyzing measured microseismic events obtained from monitoring induced hydraulic fracturing of underground geological formations, the method involving (a) postulate a geomechanical model for the region bounding the microseismic events, the model including the parameters vertical stress, reservoir pore pressure, minimum horizontal stress and the orthogonal horizontal stress, (b) select a microseismic event and (c) for the selected microseismic event assume an associated slippage plane with a postulated orientation, (d) apply the geomechanical model to the postulated orientation to determine the resulting shear stress and normal stress applied to the postulated orientation, (e) repeat steps (c) and (d) to produce a number of postulated slippage planes each with their own shear stress and normal stress attributable to them, (f) select the fracture plane having the highest ratio of shear stress to normal stress as being the fracture plane most likely to be representative of a real slippage plane cons
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: July 21, 2020
    Assignee: WESTERNGECO L.L.C.
    Inventor: Michael John Williams
  • Patent number: 10689970
    Abstract: A method for estimating downhole pressure in wells during a treatment procedure. A pressure head in a treatment well may be determined without requiring downhole sensors. The method for measuring downhole pressure may be used in long horizontal wells. By improving the accuracy of such pressure head estimates and providing the data substantially in real time, the data can also be used to control the treatment being applied to the well. The pressure head may be determined by detecting pump harmonics at a detector, typically positioned outside of the well and/or not in direct contact with the fluid in the well. The detector may be a microseismic array.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: June 23, 2020
    Assignee: SCHLUMBERGER TECHNOLOGY CORPORATION
    Inventor: Michael John Williams
  • Patent number: 10606679
    Abstract: An apparatus includes processor circuitry to perform data processing operations. Interface circuitry forms a connection to a plurality of other apparatuses and receives a foreign exception message indicative of a foreign exception event having been triggered on one of the other apparatuses. In response to receiving the foreign exception message, the interface circuitry forwards the foreign exception message to a set of the plurality of other apparatuses.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: March 31, 2020
    Assignee: Arm Limited
    Inventors: Anitha Kona, Michael John Williams, John Michael Horley, Alasdair Grant
  • Publication number: 20200050288
    Abstract: An apparatus for generating a graphical representation of a content display in a virtual reality environment, comprising: controller circuitry configured to determine a position of a device relative to a virtual reality headset in the real world, and when the device is at a predetermined position in front of the virtual reality headset, the controller circuitry is further configured to: generate a graphical representation of a content display in the virtual reality environment, the position of the graphical representation in the virtual reality environment being determined by the real world position of the device in front of the virtual reality headset, wherein the size of the graphical representation of a content display is changed in dependence on the position of the distance between the virtual reality headset and the device, wherein, in response to a user input, the controller circuitry is configured to: lock the position of the graphical representation of the content display in the virtual reality enviro
    Type: Application
    Filed: September 12, 2017
    Publication date: February 13, 2020
    Applicant: Sony Corporation
    Inventors: Michael John WILLIAMS, Paul Edward PRAYLE, Michael GOLDMAN, William Jack LEATHERS-SMITH
  • Patent number: 10554027
    Abstract: A protective cover for cable connectors and methods of fabricated the protective cover. The protective cover comprises a tube open at one end and substantially closed at the opposed end by an end cap. The end cap bears at least one opening formed therein. The protective cover has a foil outer layer, a soft felt inner layer, and an insulating fiberglass core between the outer and inner layers. The tube is made by overlappingly rolling and bonding a section of foil-backed fiberglass. The end cap may be separately made, made as part of the pattern for the tube, or may be formed by cutting pointed teeth into one end of the tube pattern and bonding them generally perpendicularly to the length of the tube.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: February 4, 2020
    Assignee: Electrolock, Inc.
    Inventors: Michael E. Lester, Michael John Williams, Matthew John Williams
  • Publication number: 20190370149
    Abstract: An apparatus and method are provided for generating and processing a trace stream indicative of instruction execution by processing circuitry. An apparatus has an input interface for receiving instruction execution information from the processing circuitry indicative of a sequence of instructions executed by the processing circuitry, and trace generation circuitry for generating from the instruction execution information a trace stream comprising a plurality of trace elements indicative of execution by the processing circuitry of instruction flow changing instructions within the sequence.
    Type: Application
    Filed: August 9, 2017
    Publication date: December 5, 2019
    Inventors: François Christopher Jacques BOTMAN, Thomas Christopher GROCUTT, John Michael HORLEY, Michael John WILLIAMS, Michael John GIBBS