Abstract: An apparatus includes processor circuitry to perform data processing operations. Interface circuitry forms a connection to a plurality of other apparatuses and receives a foreign exception message indicative of a foreign exception event having been triggered on one of the other apparatuses. In response to receiving the foreign exception message, the interface circuitry forwards the foreign exception message to a set of the plurality of other apparatuses.

Abstract: An apparatus and method are provided to control assertion of a trigger signal to processing circuitry. The apparatus has evaluation circuitry to receive program instruction execution information indicative of a program instruction executed by the processing circuitry, which is arranged to perform an evaluation operation to determine with reference to evaluation information whether the program instruction execution information indicates presence of a trigger condition. Trigger signal generation circuitry is used to assert a trigger signal to the processing circuitry in dependence on whether the trigger condition is determined to be present. Further, filter circuitry is arranged to receive event information indicative of at least one event occurring within the processing circuitry, and is arranged to determine with reference to filter control information and that event information whether a qualifying condition is present.

Abstract: A data processing apparatus is provided that includes monitor circuitry to produce local trace data indicating behaviour of the data processing apparatus. Interface circuitry communicates with a second data processing apparatus and encoding circuitry produces an encoded instruction to cause the local trace data to be stored in storage circuitry of the second data processing apparatus or to be output at output circuitry of the second data processing apparatus. The interface circuitry transmits the encoded instruction to the second data processing apparatus.

Abstract: A data processing apparatus (4) includes processing circuitry (6) for executing program instructions that form part of a transaction which executes to generate speculative updates and to commit the speculative updates if the transaction completes without a conflict. Instruction sampling circuitry (44) captures instruction diagnostic data (IDD) relating to execution of a sampled instruction. Transaction tracking circuitry (46) detects if the sampled instruction is within a transaction and if so, tracks whether the speculative updates associated with the transaction are committed and captures transaction diagnostic data (TDD) indicative of whether or not the speculative updates were committed. Thus, both instruction diagnostic data relating to a sampled instruction and transaction diagnostic data relating to the fate of a transaction containing a sampled instruction are captured.

Abstract: A data processing apparatus comprises a processing element having associated memory storage and one or more registers, the processing element being configured to perform processing activities in two or more security modes so as to inhibit a processing activity performed in one of the security modes from accessing at least some information associated with a processing activity performed in another of the security modes; in which the processing element is configured, in response to a function call causing a branch from a processing activity in a first security mode to a processing activity in a second security mode, to store the contents of one or more of the registers in the memory storage and, in response to a branch return to the first security mode, to retrieve the register contents from the memory storage; and trace apparatus configured to generate items of trace data indicative of processing activities of the processing element; in which the trace apparatus is configured to detect a branch return operatio

Abstract: An apparatus includes processing circuitry to process instructions, some of which may require addresses to be translated. The apparatus also includes address translation circuitry to translate addresses in response to instruction processed by the processing circuitry. Furthermore, the apparatus also includes translation latency measuring circuitry to measure a latency of at least part of an address translation process performed by the address translation circuitry in response to a given instruction.

Abstract: There is provided an apparatus comprising processing circuitry to execute a transaction comprising a number of program instructions that execute to generate updates to state data, to commit the updates if the transaction completes without a conflict, and to generate trace control signals during execution of the number of program instructions. The processing circuitry uses at least one resource during execution of the program instructions. Transaction trace circuitry generates trace items in response to the trace control signals. In response to the trace control signals indicating that a change in a usage level of the at least one resource has occurred during execution of the program instructions, the transaction trace circuitry generates at least one trace item that indicates the usage level of the at least one resource.

Abstract: A protective cover for cable connectors and methods of fabricated the protective cover. The protective cover comprises a tube open at one end and substantially closed at the opposed end by an end cap. The end cap bears at least one opening formed therein. The protective cover has a foil outer layer, a soft felt inner layer, and an insulating fiberglass core between the outer and inner layers. The tube is made by overlappingly rolling and bonding a section of foil-backed fiberglass. The end cap may be separately made, made as part of the pattern for the tube, or may be formed by cutting pointed teeth into one end of the tube pattern and bonding them generally perpendicularly to the length of the tube.

Abstract: An image processing method includes partitioning an image under test to form a plurality of contiguous image segments having similar image properties, deriving feature data from a subset including one or more of the image segments, and comparing the feature data from the subset of image segments with feature data derived from respective image segments of one or more other images so as to detect a similarity between the image under test and the one or more other images.

Abstract: A data processing system (2) supports non-speculative execution of vector load instructions that perform at least one contingent load of a data value. Fault detection circuitry (26) serves to detect whether a contingent load is fault-generating contingent load or a fault-free contingent load. Contingent load suppression circuitry (28) detects and suppresses a fault-free contingent load that matches a predetermined criteria that may result in an undesired change of architectural state (undesired side-effect). Examples of such predetermined criteria are that the contingent load is to a non-memory device or that the contingent load will trigger a diagnostic response such as entry of a halting debug halting mode or triggering of a debug exception.

Abstract: An apparatus and method are provided for controlling debugging of program instructions executed on processing circuitry, where the program instructions include a transaction comprising a number of program instructions that execute to generate updates to state data, with the processing circuitry then committing the updates if the transaction completes without a conflict. In addition to the processing circuitry, the apparatus has control storage for storing stepping control data used to control operation of the processing circuitry. The processing circuitry is responsive to the stepping control data having a first value to operate in a single stepping mode, where the processing circuitry initiates a debug event following execution of each instruction.

Abstract: An apparatus for generating a virtual reality environment comprising: controller circuitry configured to: insert a captured image of an object in the virtual reality environment; move the captured image within the virtual reality environment; pause the movement of the captured image in the virtual reality environment; generate a rendered representation of at least part of the captured image; replace the at least part of the captured image with the rendered representation in the virtual reality environment; and move the rendered representation within the virtual reality environment.

Abstract: A data processing apparatus is provided having a hierarchy of layers comprising at least two data processing layers, each data processing layer configured to receive data and to generate processed data for passing to a next lower layer in said hierarchy, according to a protocol specific to that data processing layer. Each data processing layer is configured intermittently to add synchronization information to its processed data, the synchronization information providing semantic information required to interpret the processed data. Each data processing layer is further configured to output its synchronization information in response to a synchronization request signal received from a lower layer in said hierarchy, and at least one data processing layer is configured, when outputting its synchronization information, to issue its synchronization request signal to a higher layer in the hierarchy.

Abstract: A method for estimating downhole pressure in wells during a treatment procedure. A pressure head in a treatment well may be determined without requiring downhole sensors. The method for measuring downhole pressure may be used in long horizontal wells. By improving the accuracy of such pressure head estimates and providing the data substantially in real time, the data can also be used to control the treatment being applied to the well. The pressure head may be determined by detecting pump harmonics at a detector, typically positioned outside of the well and/or not in direct contact with the fluid in the well. The detector may be a microseismic array.

Abstract: An image processing method includes partitioning an image under test to form a plurality of contiguous image segments having similar image properties, deriving feature data from a subset including one or more of the image segments, and comparing the feature data from the subset of image segments with feature data derived from respective image segments of one or more other images so as to detect a similarity between the image under test and the one or more other images.

Abstract: An information processing apparatus, comprising: receiver circuitry configured to receive i) a video stream comprising a plurality of images, each image containing at least one object located at a position in a plane and the image having associated image timing information indicating its temporal position in the video stream and ii) a stream of object tracking information each having associated object timing information indicating its temporal position in the stream of object tracking information wherein the stream of object tracking information corresponds to the video stream and separately defines the position of the object in the plane captured in each image in the video stream; and controller circuitry configured to perform pattern matching on the position of each of the objects in the video stream and the object tracking information, and when there is a closest matching position, synchronising the image timing information and the object timing information.

Abstract: An apparatus and method are provided for controlling debugging of program instructions that include a transaction, where the transaction is executed on processing circuitry and comprises a number of program instructions that execute to generate updates to state data, and where those updates are only committed if the transaction completes without a conflict. In addition to the processing circuitry, the apparatus has control storage for storing at least one watchpoint identifier, and the processing circuitry is then arranged, when detecting a watchpoint match condition with reference to the at least one watchpoint identifier during execution of a program instruction within the transaction, to create a pending watchpoint debug event. The processing circuitry is then responsive to execution of the transaction finishing to initiate a watchpoint debug event for the pending watchpoint debug event.

Abstract: A data processing system supporting execution of transactions comprising one or more program instructions that execute to generate speculative updates is provided. The speculative updates are committed in normal operation if the transaction completes without a conflict. Start of execution of a transaction may be detected and execution diverted to be performed by software emulation rather than direct execution by the processing hardware. The software emulation may store data representing one or more versions of the speculative updates generated during the emulation. The software emulation may also detect conflicts with the transaction being emulated. In order to facilitate modifying the behaviour of other parts of the system interacting with a transaction under investigation, a non-standard response signal may be returned in response to a detected memory access request to a transaction being emulated.

Abstract: A data processing apparatus (4) includes processing circuitry (6) for executing program instructions that form part of a transaction which executes to generate speculative updates and to commit the speculative updates if the transaction completes without a conflict. Instruction sampling circuitry (44) captures instruction diagnostic data (IDD) relating to execution of a sampled instruction. Transaction tracking circuitry (46) detects if the sampled instruction is within a transaction and if so, tracks whether the speculative updates associated with the transaction are committed and captures transaction diagnostic data (TDD) indicative of whether or not the speculative updates were committed. Thus, both instruction diagnostic data relating to a sampled instruction and transaction diagnostic data relating to the fate of a transaction containing a sampled instruction are captured.

Abstract: A data processing apparatus has processing circuitry which can execute instructions at one of several privilege levels. A plurality of performance monitoring circuits are included. In response to an instruction executed at a first privilege level, first configuration data can be set for controlling performance monitoring by a first subset of performance monitoring circuits. A disable control flag can be set in response to an instruction executed at a second privilege level higher than the first privilege level. If the disable control flag has a predetermined value then performance monitoring control circuitry disables performance monitoring by the first subset of performance monitoring circuits while the processing circuitry is executing instructions at the second privilege level.