Abstract: Disclosed herein is an interaction summarization system for automatically generating summary output. The interaction summarization system generates a transcript from an interaction including content, the content including at least one of written text, audio speech, non-word symbols, metadata, silences, language characteristics, or acoustic characteristics, wherein the content is attributed to a participant in the interaction, and generates an interaction summary of the transcript using at least one of an extractive machine learning summarization model or an abstractive machine learning summarization model that summarizes the content of the interaction.

Abstract: Disclosed herein is an interaction summarization system for automatically generating summary output. The interaction summarization system generates a transcript from an interaction including content, the content including at least one of written text, audio speech, non-word symbols, metadata, silences, language characteristics, or acoustic characteristics, wherein the content is attributed to a participant in the interaction, and generates an interaction summary of the transcript using at least one of an extractive machine learning summarization model or an abstractive machine learning summarization model that summarizes the content of the interaction.

Abstract: Disclosed herein is a method for generating insights from words and phrases mapped in high-dimensional space. The method includes obtaining a plurality of communications. The plurality of communications comprise a plurality of words and phrases. Further, the method includes obtaining a model configured through training to cluster word representations of the plurality of communications. The method also includes applying a constraint to at least a group of the plurality of communications to obtain at least one modified group. The constraint is at least one of a keyword, a phrase, or groupings of words in phrases. Once the modified group is determined, the method proceeds to representing the at least one modified group into word representations then determining a category for the at least one modified group.

Abstract: Systems and methods may provide a graphics processor that may identify operating conditions under which certain floating point instructions may utilize power to fewer hardware resources compared to when the instructions are executing under other operating conditions. The operating conditions may be determined by examining operands used in a given instruction, including the relative magnitudes of the operands and whether the operands may be taken as equal to certain defined values. The floating point instructions may include instructions for an addition operation, a multiplication operation, a compare operation, and/or a fused multiply-add operation.

Abstract: Methods and apparatus relating to mid-thread pre-emption with software assisted context switch are described. In an embodiment, one or more threads executing on a Graphics Processing Unit (GPU) are stopped at an instruction level granularity in response to a request to pre-empt the one or more threads. The context data of the one or more threads is copied to memory in response to completion of the one or more threads at the instruction level granularity and/or one or more instructions. Other embodiments are also disclosed and claimed.

Abstract: Systems and methods may provide a graphics processor that may identify operating conditions under which certain floating point instructions may utilize power to fewer hardware resources compared to when the instructions are executing under other operating conditions. The operating conditions may be determined by examining operands used in a given instruction, including the relative magnitudes of the operands and whether the operands may be taken as equal to certain defined values. The floating point instructions may include instructions for an addition operation, a multiplication operation, a compare operation, and/or a fused multiply-add operation.

Abstract: Methods and apparatus relating to mid-thread pre-emption with software assisted context switch are described. In an embodiment, one or more threads executing on a Graphics Processing Unit (GPU) are stopped at an instruction level granularity in response to a request to pre-empt the one or more threads. The context data of the one or more threads is copied to memory in response to completion of the one or more threads at the instruction level granularity and/or one or more instructions. Other embodiments are also disclosed and claimed.

Abstract: A context-free (stateless) dataport may allow multiple processors to perform read and write operations on a shared memory. The operations may include, for example, structured data operations such as image and video operations. The dataport may perform addressing computations associated with block memory operations. Therefore, the dataport may be able, for example, to relieve the processors that it serves from this duty. The dataport may be accessed using a message interface that may be implemented in a standard and generalized manner and that may therefore be easily transportable between different types of processors.

Abstract: A context-free (stateless) dataport may allow multiple processors to perform read and write operations on a shared memory. The operations may include, for example, structured data operations such as image and video operations. The dataport may perform addressing computations associated with block memory operations. Therefore, the dataport may be able, for example, to relieve the processors that it serves from this duty. The dataport may be accessed using a message interface that may be implemented in a standard and generalized manner and that may therefore be easily transportable between different types of processors.

Abstract: A context-free (stateless) dataport may allow multiple processors to perform read and write operations on a shared memory. The operations may include, for example, structured data operations such as image and video operations. The dataport may perform addressing computations associated with block memory operations. Therefore, the dataport may be able, for example, to relieve the processors that it serves from this duty. The dataport may be accessed using a message interface that may be implemented in a standard and generalized manner and that may therefore be easily transportable between different types of processors.

Abstract: A method includes storing a plurality of data RAM, holding information for all outstanding requests forwarded to a next-level memory subsystem, clearing information associated with a serviced request after the request has been fulfilled, determining if a subsequent request matches an address supplied to one or more requests already in-flight to the next-level memory subsystem, matching fulfilled requests serviced by the next-level memory subsystem to at least one requester who issued requests while an original request was in-flight to the next level memory subsystem, storing information specific to each request comprising a set attribute and a way attribute configured to identify where the returned data should be held in the data RAM once the data is returned, the information specific to each request further including at least one of thread ID, instruction queue position and color, and scheduling hit and miss data returns.

Abstract: Thread to thread communication is provided. A first thread registers with a gateway for receiving communication. Registration includes identifying a location for receiving messages. The gateway maps message payloads received from second threads to the location of the first thread. The first thread detects a payload in the location and consumes it for processing.

Abstract: Thread to thread communication is provided. A first thread registers with a gateway for receiving communication. Registration includes identifying a location for receiving messages. The gateway maps message payloads received from second threads to the location of the first thread. The first thread detects a payload in the location and consumes it for processing.

Abstract: Techniques are described that can be used to ensure ordered computation and/or retirement of threads in a multithreaded environment. Threads may contain bundled instances of work, each with unique ordering restrictions relative to other instances of work packaged in other threads in the system. When applied to 3D graphics, video and image processing domains allow unrestricted processing of threads until reaching their critical sections. Ordering may be required prior to executing critical sections and beyond.

Abstract: Thread to thread communication is provided. A first thread registers with a gateway for receiving communication. Registration includes identifying a location for receiving messages. The gateway maps message payloads received from second threads to the location of the first thread. The first thread detects a payload in the location and consumes it for processing.

Abstract: Thread to thread communication is provided. A first thread registers with a gateway for receiving communication. Registration includes identifying a location for receiving messages. The gateway maps message payloads received from second threads to the location of the first thread. The first thread detects a payload in the location and consumes it for processing.

Abstract: Methods, apparatus and computer readable medium are described that compress and/or decompress digital images in a lossless or a lossy manner. In some embodiments, a display controller may quantize pels of a digital image and may identify runs of successive quantized pels which are equal. The display controller may generate a symbol to represent an identified run of pels. The symbol may comprise a run length and a quantized pel that may be used to reconstruct the run of pels. The symbol may further comprise an error vector for each of the pels of the run that may be used to further reconstruct the run of pels.

Abstract: Methods, apparatus and computer readable medium are described that compress and/or decompress a digital image in a lossless or a lossy manner. In some embodiments, a display controller may compress a digital image by generating a symbol for each pel of the digital image. In particular, the symbol may represent a pel via a match vector and a channel error vector. The match vector may indicate which quantized channels of the pel matched quantized channels of a previous pel. Further, the channel error vector may comprise a lossless or lossy channel for each quantized channel of the pel that did not match a corresponding quantized channel of the previous pel. The channel error may also comprise a lossless or lossy channel error for each quantized channel of the pel that matched a corresponding quantized channel of the previous pel.

Abstract: According to one embodiment, the present disclosure generally provides a method for improving the performance of a cache of a processor. The method may include storing a plurality of data in a data Random Access Memory (RAM). The method may further include holding information for all outstanding requests forwarded to a next-level memory subsystem. The method may also include clearing information associated with a serviced request after the request has been fulfilled. The method may additionally include determining if a subsequent request matches an address supplied to one or more requests already in-flight to the next-level memory subsystem. The method may further include matching fulfilled requests serviced by the next-level memory subsystem to at least one requester who issued requests while an original request was in-flight to the next level memory subsystem.

Abstract: According to some embodiments, determining a new value to be pushed onto a hardware stack having n entries is determined. Each entry in the stack may include a data portion and an associated counter. If the new value equals the data portion of the entry associated with a current top of stack pointer, the counter associated with that entry is incremented. If the new value does not equal the data portion associated with the current top of stack pointer, the new value is stored in the data portion of the next entry and the current top of stack pointer is advanced.