Patents by Inventor Michael K. Dwyer

Michael K. Dwyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7219213
    Abstract: According to some embodiments, a evaluation unit may be provided for Single Instruction, Multiple Data (SIMD) execution engine flag registers. For example, a horizontal evaluation unit might perform evaluation operations across multiple vectors being processed by the SIMD execution engine. According to some embodiments, a vertical evaluation unit might perform evaluation operations across multiple flag registers.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: May 15, 2007
    Assignee: Intel Corporation
    Inventors: Michael K. Dwyer, Hong Jiang
  • Patent number: 7212676
    Abstract: Methods, apparatus and computer readable medium are described that compress and/or decompress a digital image in a lossless or a lossy manner. In some embodiments, a display controller may compress a digital image by generating a symbol for each pel of the digital image. In particular, the symbol may represent a pel via a match vector and a channel error vector. The match vector may indicate which quantized channels of the pel matched quantized channels of a previous pel. Further, the channel error vector may comprise a lossless or lossy channel for each quantized channel of the pel that did not match a corresponding quantized channel of the previous pel. The channel error may also comprise a lossless or lossy channel error for each quantized channel of the pel that matched a corresponding quantized channel of the previous pel.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: May 1, 2007
    Assignee: Intel Corporation
    Inventors: Michael K. Dwyer, Thomas A. Piazza
  • Publication number: 20040126032
    Abstract: Methods, apparatus and computer readable medium are described that compress and/or decompress a digital image in a lossless or a lossy manner. In some embodiments, a display controller may compress a digital image by generating a symbol for each pel of the digital image. In particular, the symbol may represent a pel via a match vector and a channel error vector. The match vector may indicate which quantized channels of the pel matched quantized channels of a previous pel. Further, the channel error vector may comprise a lossless or lossy channel for each quantized channel of the pel that did not match a corresponding quantized channel of the previous pel. The channel error may also comprise a lossless or lossy channel error for each quantized channel of the pel that matched a corresponding quantized channel of the previous pel.
    Type: Application
    Filed: December 30, 2002
    Publication date: July 1, 2004
    Inventors: Michael K. Dwyer, Thomas A. Piazza
  • Publication number: 20040126031
    Abstract: Methods, apparatus and computer readable medium are described that compress and/or decompress digital images in a lossless or a lossy manner. In some embodiments, a display controller may quantize pels of a digital image and may identify runs of successive quantized pels which are equal. The display controller may generate a symbol to represent an identified run of pels. The symbol may comprise a run length and a quantized pel that may be used to reconstruct the run of pels. The symbol may further comprise an error vector for each of the pels of the run that may be used to further reconstruct the run of pels.
    Type: Application
    Filed: December 30, 2002
    Publication date: July 1, 2004
    Inventors: Michael K. Dwyer, Thomas A. Piazza
  • Patent number: 6369813
    Abstract: The present invention is directed to a method and apparatus for processing normalized meshes. The normalized meshes are formed by N polygons which have M vertices. M vertex coordinates are stored in a vertex array corresponding to the M vertices of the N polygons. N polygon indices are stored in an index array. Each of the N polygon indices references a predetermined number of the M vertex coordinates. A first subset of the index array having N1 polygon indices is determined. A second subset of the vertex array is selected such that the second subset contains M1 vertex coordinates corresponding entirely to the N1 polygon indices in the first subset. The second subset defines a window having a small size relative to the vertex array. The M1 vertex coordinates in the second subset are processed to generate processed data. The processed data are then concurrently sent to a graphics processor in an on-line manner.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: April 9, 2002
    Assignee: Intel Corporation
    Inventors: Vladimir Pentkovski, Deep Buch, Michael K. Dwyer, Hsien-Hsin Lee, Hsien-Cheng E. Hsieh
  • Publication number: 20020008698
    Abstract: The present invention is directed to a method and apparatus for processing normalized meshes. The normalized meshes are formed by N polygons which have M vertices. M vertex coordinates are stored in a vertex array corresponding to the M vertices of the N polygons. N polygon indices are stored in an index array. Each of the N polygon indices references a predetermined number of the M vertex coordinates. A first subset of the index array having N1 polygon indices is determined. A second subset of the vertex array is selected such that the second subset contains M1 vertex coordinates corresponding entirely to the N1 polygon indices in the first subset. The second subset defines a window having a small size relative to the vertex array. The M1 vertex coordinates in the second subset are processed to generate processed data. The processed data are then concurrently sent to a graphics processor in an on-line manner.
    Type: Application
    Filed: June 30, 1998
    Publication date: January 24, 2002
    Inventors: VLADIMIR PENTKOVSKI, DEEP BUCH, MICHAEL K. DWYER, HSIEN-HSIN LEE, HSIEN-CHENG E. HSIEH