Abstract: A system and method is provided for applying a developer to a photoresist material layer disposed on a semiconductor substrate. The developer system and method employ a developer plate having a plurality of a application apertures for dispensing developer and a plurality of exit apertures for allowing excess developer to be removed from between the developer plate and the photoresist material layer. Preferably, the developer plate has a bottom surface with a shape that is similar to the wafer. The developer plate is disposed above the wafer and substantially and/or completely surrounds the top surface of the wafer during application of the developer. A small gap is formed between the wafer and the bottom surface of the developer plate. The wafer and the developer plate form a parallel plate pair, such that the gap can be made small enough so that the developer fluid quickly fills the gap with excess developer exiting through the exit apertures.

Abstract: The present invention involves a method for fabricating interconnecting lines and vias. According to the invention, copper is grown from a seed layer to substantially fill openings in a two layer structure wherein the two layers are independently either dielectric or resist layers. According to one aspect of the invention, first and second resist layers are formed into a dual damascene structure. Copper is grown by plating from the copper seed layer to form copper features that fill the pattern gaps.

Abstract: A method is provided of forming lines with spaces between memory cells below a minimum printing dimension of a photolithographic tool set. In one aspect of the invention, lines and spaces are formed in a first polysilicon layer that forms floating gates of flash memory cells. STI regions are formed between adjacent memory cells in a substrate to isolate the cells from one another. The first polysilicon layer is deposited over the substrate covering the STI regions. The first polysilicon layer is then planarized by a CMP process or the like to eliminate overlay issues associated with the STI regions. A hard mask layer is deposited over the first polysilicon layer and a first space dimension d1 etched between adjacent memory cells. A conformal nitride layer is deposited over the hard mask layer and an etch step performed to form nitride side walls adjacent the spaces.

Abstract: One aspect of the present invention relates to a method of cleaning a patterned photoresist clad structure involving the steps of contacting the patterned photoresist clad structure with an alcohol vapor comprising at least one compound having the Formula ROH, wherein R is a hydrocarbon group comprising from 4 to about 8 carbon atoms; condensing the alcohol vapor on the patterned photoresist clad structure; and removing the condensed alcohol vapor from the patterned photoresist clad structure. Another aspect of the present invention involves the use of an alcohol vapor having a boiling point from about 102° C. to about 175° C. Yet another aspect of the present invention involves the use of an alcohol vapor having a flash point from about 15° C. to about 80° C.

Abstract: The present invention is directed to a method and a system for non-destructively, efficiently and accurately detecting asymmetry in the profile of a feature formed on a wafer during the process of semiconductor fabrication. The method encompasses directing a beam of light or radiation at a feature and detecting a reflected beam associated therewith. Data associated with the reflected beam is correlated with data associated with known feature profiles to ascertain profile characteristics associated with the feature of interest. Using the profile characteristics, an asymmetry of the feature is determined which is then used to generate feedback or feedforward process control data to compensate for or correct such asymmetry in subsequent processing.

Abstract: The present invention relates to systems and methods to regulate spacer deposition. The present invention employs a spacer deposition controller to control a spacer deposition component that deposits a spacer on a portion of a wafer. During and/or after spacer deposition, light can be directed at the spacer, wherein light reflected from the spacer is measured to determine parameters associated with the spacer deposition process. A processor operatively coupled to a measurement system and the spacer deposition controller utilizes the parameters to determine if the spacer process is proceeding in a suitable manner via comparing the measured parameters with stored acceptable parameters. If it is determined that the spacer deposition process is not proceeding as desired, then the measured parameters can be employed by the spacer deposition controller to adjust the spacer deposition process on the portion of the wafer and on subsequent portions of wafers.

Abstract: The present invention relates to systems and methods for increasing the hydrophobicity of patterned resists. In one embodiment, the present invention relates to a method of processing an ultra-thin resist, involving depositing the ultra-thin photoresist over a semiconductor substrate; irradiating the ultra-thin resist with electromagnetic radiation; developing the ultra-thin resist with a developer to form a patterned resist, the patterned resist having a surface with a first hydrophobicity; contacting the patterned resist with a transition solvent to provide the surface of the patterned resist with a second hydrophobicity, wherein the second hydrophobicity is greater than the first hydrophobicity and contact of the patterned resist with the transition is conducted between developing the ultra-thin resist and rinsing patterned resist; and rinsing the patterned resist having the second hydrophobicity with an aqueous solution.

Abstract: A system for regulating heating temperature of a material is provided. The material may be a photoresist, a top or bottom anti-reflective coating, a low K dielectric material, SOG or other spin-on material, for example. The system includes a plurality of lamps and optical fibers, each optical fiber directing radiation to and heating a respective portions of a bakeplate on which the material is to be placed. In one embodiment, the temperature at various locations on the material placed on the bakeplate is determined and the heating rates are controlled in response to those measurements. In another aspect of the invention, the temperature at various portions of the bakeplate is determined and controlled. In this latter aspect, uniform heating of the material is a consequence of uniform bakeplate temperature.

Abstract: A system for regulating temperature of a post exposure baking process is provided. The system includes one or more light sources, each light source directing light to one or more gratings being baked and hardened on a wafer. Light reflected from the gratings is collected by a measuring system, which processes the collected light. Light passing through the gratings may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the baking and hardening of the respective portions of the wafer. The measuring system provides baking and hardening related data to a processor that determines the baking and hardening of the respective portions of the wafer. The system also includes a plurality of temperature controlling devices, each such device corresponds to a respective portion of the wafer and provides for the heating and/or cooling thereof.

Abstract: A system and method is provided for applying a developer to a photoresist material wafer disposed on a semiconductor substrate. The developer system and method employ a developer plate having a plurality of a apertures for dispensing developer. Preferably, the developer plate has a bottom surface with a shape that is similar to the wafer. The developer plate is disposed above the wafer and substantially and/or completely surrounds the top surface of the wafer during application of the developer. A small gap is formed between the wafer and the bottom surface of the developer plate. The wafer and the developer plate form a parallel plate pair, such that the gap can be made small enough so that the developer fluid quickly fills the gap. The developer plate is disposed in very close proximity with respect to the wafer, such that the developer is squeezed between the two plates thereby spreading evenly the developer over the wafer.

Abstract: The present invention provides SEM calibration standards, and associated SEM systems and SEM calibration methods, that are self-cleaning with respect to electron beam deposited carbon. The calibration standards have coatings containing a transition metal oxide. The coatings facilitate oxidation of deposited carbon, whereby carbon buildup can be stopped or reversed. By providing a mechanism to mitigate carbon buildup, calibration standards provided by the present invention achieve high accuracy, high durability, and low cost.

Abstract: A system for regulating the time and temperature of a development process is provided. The system includes one or more light sources, each light source directing light to one or more gratings being developed on a wafer. Light reflected from the gratings is collected by a measuring system, which processes the collected light. Light passing through the gratings may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the progress of development of the respective portions of the wafer. The measuring system provides progress of development related data to a processor that determines the progress of development of the respective portions of the wafer. The system also includes a plurality of heating devices, each heating device corresponds to a respective portion of the developer and provides for the heating thereof. The processor selectively controls the heating devices so as to regulate temperature of the respective portions of the wafer.

Abstract: A system for regulating a gaseous phase chemical trim process is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the dimensions achieved at respective portions of the wafer. The measuring system provides trimming related data to a processor that determines the acceptability of the trimming of the respective portions of the wafer. The system also includes one or more trimming devices, each such device corresponding to a portion of the wafer and providing for the trimming thereof. The processor selectively controls the trimming devices to regulate trimming of the portions of the wafer.

Abstract: One aspect of the present invention relates to a method for reducing resist residue defects on a wafer structure. The method involves providing a semiconductor structure having a photoresist, the photoresist comprising open areas and circuit areas thereon; irradiating the open areas and circuit areas through a first photomask with a first energy dose to effect an image-wise pattern in the photoresist; irradiating the open areas of the photoresist through a second photomask with a second energy dose; and developing the photoresist.

Abstract: A system for regulating spacer deposition is provided. At least one spacer deposition component deposits spacer on a portion of a wafer. A spacer deposition controller regulates the at least one spacer deposition component. A system for directing light directs light to the at least one spacer and collects light reflected from the portion of the wafer. A measuring system measures thickness parameters associated with the deposited spacer. A processor is operatively coupled to the measuring system and the spacer deposition controller, wherein the processor receives the measured data from the measuring system, analyzes the measured data by comparing the measured data to stored acceptable spacer thickness values to determine necessary adjustments to the spacer deposition component via the spacer deposition controller to facilitate regulating spacer thickness on the portion of the wafer and on subsequent portions of wafers.

Abstract: The present invention relates to a method for fabricating interconnecting lines and vias in a layer of insulating material. A via is formed in the layer of insulating material. A protective material is formed so as to be conformal to at least edges and sidewalls of the via, the protective material facilitating shielding of at least the edges and sidewalls of the via from a trench etch step. The trench etch step is performed to form a trench opening in the insulating material. The via and trench are filled with a conductive metal.

Abstract: A method and system for providing an alignment mark for a thin layer in a semiconductor device is disclosed. The semiconductor device includes at least one alternative part having a first thickness greater than a second thickness of the thin layer. The method and system include providing the thin layer and providing the alignment mark for the thin layer in the at least one alternative part. The alignment mark has a depth that is greater than the second thickness of the thin layer. In one aspect, the method and system include providing a mask for the thin layer. The mask includes an alignment mark portion that covers the at least one alternative part and that is for providing the alignment mark. In this aspect, the method and system also include removing a portion of the at least one alternative part to provide the alignment mark in the at least one alternative part.

Abstract: The present invention provides systems, methods, and standards for calibrating nano-measuring devices. Calibration standards of the invention include carbon nanotubes and methods of the invention involve scanning carbon nanotubes using nano-scale measuring devices. The widths of the carbon nanotube calibration standards are known with a high degree of accuracy. The invention allows calibration of a wide variety of nano-scale measuring devices, taking into account many, and in some cases all, of the systematic errors that may affect a nano-scale measurement. The invention may be used to accurately calibrate line width, line height, and trench width measurements and may be used to precisely characterize both scanning probe microscope tips and electron microscope beams.

Abstract: A system and method is provided that facilitates the application of a uniform layer of developer material on a photoresist material layer. The system includes a nozzle adapted to apply a predetermined volume of developer material on a photoresist material layer along a linear path having a length approximately equal to the diameter of the photoresist material layer. A movement system moves the nozzle to a first position offset from a central region of the photoresist material layer for applying a first predetermined volume of developer material to the photoresist material layer while the developer material is spin coated. The movement system also moves the nozzle to a second position offset from the central region for applying a second predetermined volume of developer material to the photoresist material layer while the developer is spin coated. The first position is located on an opposite side of the central region with respect to the second position.

Abstract: The present invention relates to a system and method for calibrating a scanning electron microscope (SEM). The method comprises measuring an electrical characteristic of a calibration standard reference sample feature via a current induced by an electron beam (e-beam) and correlating the e-beam induced current measurement with an SEM measurement thereof. The correlation of the e-beam induced current and SEM measurements provides a critical dimension (CD) for the reference sample feature which can then be used to correlate SEM measurements of workpiece features. The system provides a reference sample having a measurable feature electrically connected to a probe. The probe provides an electrical measurement of the reference sample feature based on an e-beam induced current. The system further comprises a scanning electron microscope (SEM) adapted to provide an optical measurement of the reference sample feature and workpiece features.