Abstract: The present invention relates to a system and method for calibrating a scanning electron microscope (SEM). The method comprises measuring an electrical characteristic of a calibration standard reference sample feature and correlating the electrical measurement with an SEM measurement thereof. The correlation of the electrical and SEM measurements provides a critical dimension (CD) for the reference sample feature which can then be used to correlate SEM measurements of workpiece features. The system provides a reference sample having a measurable feature electrically connected to a probe. The probe provides an electrical measurement of the reference sample feature. The system further comprises a scanning electron microscope (SEM) adapted to provide an optical measurement of the reference sample feature. A processor is provided to correlate the optical and electrical measurements of the reference sample feature, whereby a reference feature CD is obtained.

Abstract: In invention provides a system for reducing or eliminating side lobes in patterned resist coatings. The system heats the resist briefly to induce the resist to flow. The system allows the resist to flow long enough for the side lobes to level, but not so long as to corrupt the resist pattern. The original resist pattern may be biased to allow for some flow during the side lobe reduction process. The invention is useful in eliminating side lobes that typically result when an attenuated phase shift mask is used to form a patterned resist coating with fine, sharp-edged features.

Abstract: A system for monitoring and controlling aperture etching in a complimentary phase shift mask is provided. The system includes one or more light sources, each light source directing light to one or more apertures etched on a mask. Light reflected from the apertures is collected by a measuring system, which processes the collected light. Light passing through the apertures may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the depth and/or width of the openings on the mask. The measuring system provides depth and/or width related data to a processor that determines the acceptability of the aperture depth and/or width. The system also includes a plurality of etching devices associated with etching apertures in the mask. The processor selectively controls the etching devices so as to regulate aperture etching.

Abstract: A system for monitoring a latent image exposed in a photo resist during semiconductor manufacture is provided. The system includes one or more light sources, each light source directing light to the latent image and/or one or more gratings exposed on one or more portions of a wafer. Light reflected from the latent image and/or the gratings is collected by a signature system, which processes the collected light. Light passing through the latent image and/or gratings may similarly be collected by the signature system, which processes the collected light. The collected light is analyzed and can be employed to generate feedback information to control the exposure. The collect light is further analyzed and can be employed to generate feed forward information that can be employed to control post exposure processes including development and baking processes.

Abstract: The present invention is directed to a system and a method for controlling a thin film formation on a moving substrate as part of a process for manufacturing an integrated circuit. The invention involves the use of scatterometry to control the thin film formation process by analyzing the thin film on the moving substrate in a periodic manner. A registration feature associated with the moving substrate can be utilized in conjunction with a signaling system to determine a position of the moving substrate, whereby a repeatable analysis of a corresponding location on the moving substrate can be performed. Scatterometry permits in-situ measurements of thin film formation progress, whereby thin film formation process conditions can be controlled in a feedback loop to obtain a targeted result. Scatterometry can also be facilitated by providing a grating pattern on a non-production portion of the substrate.

Abstract: The present invention relates to wafer alignment. A reticle is employed which includes, a design, and a first and second set of scribe marks. The first and second sets of scribe marks have an associated symmetry relative to the reticle design. The design and scribe marks are printed at selected field locations on a surface layer of the wafer. The first and second sets of scribe marks as printed at adjacent fields on the surface layer of wafer form a composite set of scribe marks. The symmetric relationship between the first and second sets of scribe marks results in the composite set of scribe marks substantially negating print errors of the marks due to reticle rotation and/or lens magnification with respect to a geometric reference point of the composite set of scribe marks. The employment of the composite set of scribe marks, such as to locate a corresponding virtual alignment mark, substantially facilitates mitigation of overlay error in wafer alignment.

Abstract: A system and method is provided that facilitates the application of a uniform layer of developer material on a photoresist material layer. The system includes a nozzle adapted to apply a predetermined volume of developer material on a photoresist material layer along a linear path having a length approximately equal to the diameter of the photoresist material layer. A movement system moves the nozzle to a first position offset from a central region of the photoresist material layer for applying a first predetermined volume of developer material to the photoresist material layer while the developer material is spin coated. The movement system also moves the nozzle to a second position offset from the central region for applying a second predetermined volume of developer material to the photoresist material layer while the developer is spin coated. The first position is located on an opposite side of the central region with respect to the second position.

Abstract: A system for monitoring and/or controlling an etch process associated with a dual damascene process via scatterometry based processing is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the etch results achieved at respective portions of the wafer. The measuring system provides etching related data to a processor that determines the desirability of the etching of the respective portions of the wafer. The system also includes one or more etching devices, each such device corresponding to a portion of the wafer and providing for the etching thereof. The processor produces a real time feed forward information to control the etch process, in particular, terminating the etch process when desired end points have been encountered.

Abstract: A system and method is provided that facilitates the application of a uniform layer of developer material on a photoresist material layer. The system includes a multiple tip nozzle and a movement system that moves the nozzle to an operating position above a central region of a photoresist material layer located on a substrate, and applies a volume of developer as the nozzle scan moves across a predetermined path. The movement system moves the nozzle in two dimensions by providing an arm that has a first arm member that is pivotable about a first rotational axis and a second arm member that is pivotable about a second rotational axis or is movable along a translational axis. The system also provides a measurement system that measures the thickness uniformity of the developed photoresist material layer disposed on a test wafer. The thickness uniformity data is used to reconfigure the predetermined path of the nozzle as the developer is applied.

Abstract: In one embodiment, the present invention relates to a method of treating a patterned resist involving providing the patterned resist having a first number of structural features, the patterned resist comprising an acid catalyzed polymer; contacting a coating containing a coating material, at least one basic compound, a photoacid generator, and a dye with the patterned resist; irradiating the coated patterned resist; permitting a deprotection region to form within an inner portion of the patterned resist; and removing the coating and the deprotection region to provide a second number of patterned resist structural features, wherein the first number is smaller than the second number.

Abstract: The present invention is directed to a system and a method for controlling a thin film formation on a moving substrate as part of a process for manufacturing an integrated circuit. The invention involves the use of scatterometry to control the thin film formation process by analyzing the thin film on the moving substrate comprising an optical indicia and a periodic analysis structure in a periodic manner. The optical indicia is spatially associated with the periodic analysis structure and is utilized in conjunction with a signaling system to determine a position of the moving substrate, whereby a repeatable analysis of a corresponding location on the moving substrate can be performed. Scatterometry permits in-situ measurements of thin film formation progress, whereby thin film formation process conditions can be controlled in a feedback loop to obtain a targeted result. Scatterometry can also be facilitated by providing a grating pattern on a non-production portion of the substrate.

Abstract: One aspect of the present invention relates to a method of forming an advanced low k material between metal lines on a semiconductor substrate, involving the steps of providing the semiconductor substrate having a plurality of metal lines thereon; depositing a spin-on material over the semiconductor substrate having the plurality of metal lines thereon; and at least one of heating or etching the semiconductor substrate whereby at least a portion of the spin-on material is removed, thereby forming the advanced low k material comprising at least one air void between the metal lines, the advanced low k material having a dielectric constant of about 2 or less.

Abstract: One aspect of the present invention relates to a method and an apparatus for rinsing a substrate during a development process to mitigate pattern collapse. The apparatus includes a bath chamber; a substrate holder disposed in the bath chamber for holding the substrate having a resist pattern formed thereon; a first nozzle for dispensing a first rinsing solution having a first density and first surface tension into the bath chamber; a second nozzle for dispensing a second rinsing solution having a second density and second surface tension, which is less than the first rinsing solution, into the bath chamber; a drain disposed in a bottom portion of the bath chamber; and a controlling system operatively coupled to the first nozzle, the second nozzle and the drain designed to regulate and coordinate the operation of the first nozzle, the second nozzle and the drain.

Abstract: A system for monitoring a latent image exposed in a photo resist during semiconductor manufacture is provided. The system includes one or more light sources, each light source directing light to the latent image and/or one or more gratings exposed on one or more portions of a wafer. Light reflected from the latent image and/or the gratings is collected by a signature system, which processes the collected light. Light passing through the latent image and/or gratings may similarly be collected by the signature system, which processes the collected light. The collected light is analyzed and can be employed to generate feedback information to control the exposure. The collect light is further analyzed and can be employed to generate feed forward information that can be employed to control post exposure processes including development and baking processes.

Abstract: The present invention involves a method for fabricating interconnecting lines and vias. According to the invention, copper is grown within the openings in a patterned coating. The patterned coating can be a resist coating or a dielectric coating. Either type of coating can be formed over a copper seed layer, whereby the seed layer is exposed within the pattern gaps. The copper seed layer can also be provided within the pattern gaps after patterning. Copper features are grown within the pattern gaps by plating. Where the patterned coating is a resist, the resist is stripped leaving the copper features in the inverse pattern image. The copper features can be coated with a diffusion barrier layer and a dielectric. The dielectric is polished to leave the dielectric filling the spaces between copper features. The invention provides copper lines and vias without the need for a dielectric or metal etching step.

Abstract: A system for monitoring and/or controlling an etch process associated with a dual damascene process via scatterometry based processing is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the etch results achieved at respective portions of the wafer. The measuring system provides etching related data to a processor that determines the desirability of the etching of the respective portions of the wafer. The system also includes one or more etching devices, each such device corresponding to a portion of the wafer and providing for the etching thereof. The processor produces a real time feed forward information to control the etch process, in particular, terminating the etch process when desired end points have been encountered.

Abstract: A system for characterizing an etch process via scatterometry based real time imaging is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the etch results achieved at respective portions of the wafer. The measuring system provides etching related data to a processor that determines the desirability of the etching of the respective portions of the wafer. The system also includes one or more etching devices, each such device corresponding to a portion of the wafer and providing for the etching thereof. The processor produces a real time etch image to characterize the progress of the etching and, in one example, produces suggested adaptations to the etch process.

Abstract: A method and system for providing a plurality of lines in a semiconductor memory device is disclosed. The method and system include providing a semiconductor substrate, providing a plurality of lines and providing an adjacent feature. The plurality of lines includes an adjacent line adjacent to the adjacent feature. The each of the plurality of lines has a line width that is substantially the same for each of the plurality of lines. The plurality of lines is preferably formed utilizing a mask to print a physical mask for the plurality of lines and the adjacent feature. The mask includes a mask assist feature between at least a first polygon for the adjacent line and at least a second polygon for the adjacent feature. The mask assist feature has a size that is sufficiently large to affect the width of the adjacent line and that is sufficiently small to prevent a corresponding feature from being printed on the physical mask.

Abstract: In one embodiment, the present invention relates to a method of treating a patterned resist involving the steps of providing the patterned resist having structural features of a first size, the patterned resist containing a polymer having a labile group; contacting a coating containing at least one cleaving compound with the patterned resist to form a thin deprotected resist layer at an interface between the patterned resist and the coating; and removing the coating and the thin deprotected resist layer leaving the patterned resist having structural features of a second size, wherein the second size is smaller than the first size.

Abstract: The invention provides systems and processes that form the inverse (photographic negative) of a patterned first coating. The patterned first coating is usually provided by a resist. After the first coating is patterned, a coating of a second material is provided thereover. The uppermost layer of the second coating is removed, where appropriate, to expose the patterned first coating. The patterned first coating is subsequently removed, leaving the second coating material in the form of a pattern that is the inverse pattern of the first coating pattern. The process may be repeated with a third coating material to reproduce the pattern of the first coating in a different material. Prior to applying the second coating, the patterned first coating may be trimmed by etching, thereby reducing the feature size and producing sublithographic features. In addition to providing sublithographic features, the invention gives a simple, efficient, and high fidelity method of obtaining inverse coating patterns.