Abstract: A system and method are provided that use a determination of bad data parity and the state of an error signal (Derr.sub.--) as a functional signal indicating a specific type of error in a particular system component. If the Derr.sub.-- signal is active, the parity error recognized by the CPU was caused by a correctable condition in a data providing device. In this instance, the processor will read the corrected data from a buffer without reissuing a fetch request. When the CPU finds a parity error, but Derr.sub.-- is not active a more serious fault condition is identified (bus error or uncorrectable multibit error) requiring a machine level interrupt, or the like. And, when no parity is found by the CPU and Derr.sub.-- is not active, then the data is known to be valid and the parity/ECC latency is eliminated, thereby saving processing cycle time.

Abstract: PowerPC external control instructions are utilized to pass a translated address to a transfer engine located in the system memory controller, together with previously transferred parameters into control registers within the memory controller. An accelerated data movement is accomplished between system memory and an input/output device with a minimum of processor overhead and bus bandwidth utilization. This method is useful for transferring large amounts of data between memory and such devices as graphics adapters or multimedia devices.

Abstract: A method and system are provided for communicating between devices. A signal is output from a first device. In response to the signal, at least one action is initiated by a second device. An indication is output of whether the second device completed the action and of whether operation of the second device is independent of the first device reoutputting the signal.

Abstract: An information handling system includes one or more processing units, a data management unit, connected to the processor data bus, to a memory system, and to a I/O bus, an address management unit, connected to the processor address bus, to the memory system, to an I/O bus, and to a system initialization storage device, storing an initialization routine and data, wherein system initialization includes, in response to an Initial Program Load Read command issued by a processor, the steps of returning initialization data to the processor if the IPL read is accepted (IPL data available) by a device attached to the processor bus; if no device attached to the processor bus responds with IPL data, passing the read IPL command to the I/O bus under control of the data management unit; if the read command is accepted by an I/O controller attached to the I/O bus, returning initialization data to the processor; if no I/O controller accepts the IPL read command, passing the read command to the system initialization storage

Abstract: An information handling system includes a system memory controller having a control register in which a bit is reserved for Doze mode control. The Doze control bit is set by system software whenever it places any processor into Doze mode. Until this bit is set, there is no wake up signal issued nor any performance lost. Whenever this control bit is set, the memory controller sends a signal to the system arbiter that informs it to issue a "wake up signal" before issuing an address bus grant, in time to satisfy the processor wake up latency. In addition, if the system arbiter receives another address bus request within a predefined time window, the "wake up signal" is held active without adding to the bus grant latency. If maximum system performance is desired (all processors out of Doze mode), the system software resets the Doze mode control bit in the memory controller, which removes the signal to the system arbiter which controls the wake up signal and removes the added latency for granting the bus.

Abstract: An efficient multiprocessor address transfer mechanism is utilized within a data processing system including a plurality of bus devices. The present invention places control of the flow of address bus operations within the system controller rather than the bus devices, e.g., a master processor. The system controller issues an address bus grant, in response to an address bus request from a particular bus device, and shortly after that issues another signal notifying the granted bus device that it must now disable the address bus. Furthermore, upon receipt of the signal indicating disablement of the address bus, other bus devices may then snoop, or sample, the address bus.

Abstract: An information handling system includes one or more processing units, a data bus management unit, connected to the processor data bus, to a memory system, and to an I/O bus, an address management unit, connected to the processor address bus, to the memory system, to the I/O bus, and one or more I/O controllers, where the address and data management units isolate the processor buses from the I/O bus and the memory system.

Abstract: An information processing system includes a plurality of bus devices coupled to at least one storage device via a bus. A first device (the "requestor") on a bus issues a request to obtain data and coherency information and monitors for the coherency information during a designated coherency response interval. A second device (the "respondant") sends a first signal during the designated coherency response interval indicating that the coherency information will be returned during a second interval, and sends a second signal providing the coherency information to the requestor during the second interval.

Abstract: A system and method which utilizes a unique bus protocol in conjunctions plural Dval.sub.-- control signals to minimize the dead time between blocks of data being transferred between components is a data processing system. The present invention introduces another latch-to-latch data valid control signal and alternates the usage of this signal during back to back data transfers from the same or different bus devices. In this manner the restore and tristate dead cycles are totally overlapped with the data transfer and the minimum possible number of dead cycle(s) is achieved between different blocks of data transfers. With the method of the present invention, data providers alternately activate the Dval.sub.-- signals and data receivers look at all Dval.sub.-- signals and if any one of them is active, then the data is considered valid and can be read.

Abstract: A multiprocessor system utilizing a plurality of bus devices coupled via a shared bus utilizes a specially coded signal to notify a bus device initiating a read or a read with intent to modify operation that the requested data, or cache line, is in a modified state within a cache of another bus device. Unlike the modified response signal, this special signal is sent along with the requested data from the one bus device to the requesting bus device, indicating that this data has priority over any data being sent from the memory system coupled to the shared bus. The present invention allows for cache-to-cache and cache-to-memory-and-cache operations.

Abstract: A photographic apparatus in which strip-shaped material is to be advanced by means of a travelling leader tape, has a carrier for the strip-shaped material, the carrier being formed with a channel. An arrangement is provided by means of which the leader tape can be sprung into the channel in response to a command signal so that a mechanical connection becomes established between the leader tape and the carrier and the latter is taken along by the travelling leader tape.