Abstract: Systems and methods configured to cancel spurs in a phase locked loop (PLL) system are provided. A method configured to cancel spurs in a PLL system includes receiving a PLL signal from the PLL system; determining an estimated spur frequency of a spur in the received PLL signal based on the received PLL signal; and canceling the spur in the received PLL signal based on the estimated spur frequency.

Abstract: A precursor rejection filter is disclosed. A digital filter is coupled to receive packets from a data source. The filter may operate in one of a first mode or a second mode. In the first mode, the filter may receive communications packets. When operating in the second mode, the filter may receive sensing packets. Furthermore, when operating in the second mode, the filter may cause a precursor of the equivalent impulse response of the transmitter to be attenuated without attenuating the main lobe of the of the equivalent impulse response of the transmitter.

Abstract: Embodiments are presented herein of apparatuses, systems, and methods for a wireless device to perform improved channel estimates for sensing applications such as ranging. The wireless device may determine noise characteristics, e.g., a spectrum of the variance of noise on a channel and may use the noise characteristics to estimate a response of an analog front end of the wireless device. The wireless device may correct a channel estimate based on the estimated response of the analog front end.

Abstract: This disclosure relates to techniques for performing ranging wireless communication in a secure manner. A first wireless device may receive a plurality of independent sequences from a second wireless device. The first wireless device may perform a combined channel estimate using the sequences. The first wireless device may estimate the distance (or angle/direction, among various possibilities) between the two devices based on the combined channel estimate.

Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.

Abstract: Embodiments are presented herein of apparatuses, systems, and methods for a wireless device to perform improved channel estimates for sensing applications such as ranging. The wireless device may determine noise characteristics, e.g., a spectrum of the variance of noise on a channel and may use the noise characteristics to estimate a response of an analog front end of the wireless device. The wireless device may correct a channel estimate based on the estimated response of the analog front end.

Abstract: Systems and methods configured to cancel spurs in a phase locked loop (PLL) system are provided. A method configured to cancel spurs in a PLL system includes receiving a PLL signal from the PLL system; determining an estimated spur frequency of a spur in the received PLL signal based on the received PLL signal; and canceling the spur in the received PLL signal based on the estimated spur frequency.

Abstract: Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry configured to, in a first mode, identify a delay element of a plurality of delay elements based on an associated delay value, and set an initial phase difference value to a phase difference value associated with the identified delay element. The processor circuitry may be further configured to, in a second mode, in a second mode, initialize the DPLL using the initial phase difference value, determine a phase error between a reference clock and a feedback clock based on the initial phase difference value, adjust an output clock signal based on the phase error.

Abstract: A device and method for a user equipment (UE) to perform packet detection using multiple receive antennas. The UE receives a first signal at two or more of the plurality of receive antennas. The UE determines a first combined signal parameter based on the first signal received at the two or more receive antennas. The UE receives a second signal at the two or more receive antennas. The UE determines a second combined signal parameter based on the second signal received at the two or more receive antennas. The UE detects a packet based on at least identifying a correlation between the first combined signal parameter and the second combined signal parameter.

Abstract: The present disclosure relates to methods and apparatuses for compensating carrier or clock signal phase fluctuations. An apparatus comprises a digital phase locked loop (210) comprising a phase error output (214) for a phase error (216) between a reference signal (218) and an output signal (212) generated by the digital phase locked loop, and a phase rotator (220) coupled to the phase error output (214) and configured to rotate a phase of a data signal based on the phase error (216).

Abstract: Some embodiments enable improved packet error rate (PER), signal to noise ratio (SNR), channel capacity, aggregated throughput, and communication range in wireless communication systems. For example, an electronic device includes a buffer that stores a first descrambled bit estimate sequence. The electronic device further includes an encoder that receives a descrambling sequence and generates an encoded descrambling sequence and a multiplier circuit that receives a bit estimate sequence and the encoded descrambling sequence and generates a second descrambled bit estimate sequence. The electronic device also includes an adder circuit that combines the first descrambled bit estimate sequence and the second descrambled bit estimate sequence and a decoder that decodes the combined descrambled bit estimate sequence.

Abstract: Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry configured to, in a first mode, identify a delay element of a plurality of delay elements based on an associated delay value, and set an initial phase difference value to a phase difference value associated with the identified delay element. The processor circuitry may be further configured to, in a second mode, in a second mode, initialize the DPLL using the initial phase difference value, determine a phase error between a reference clock and a feedback clock based on the initial phase difference value, adjust an output clock signal based on the phase error.

Abstract: A method for noise shaping includes: reducing a bit-depth of an input signal to obtain a quantized input signal; feeding a quantization error corresponding to the bit-depth reduction of the input signal into a feedback loop to the input signal, the feedback loop comprising a first quantization stage, a second quantization stage and a correction stage, both the first and second quantization stages operating at the bit-depth of the input signal and the correction stage operating at a bit-depth of the quantization error; and generating a noise-shaped output signal at lower clock rate than the input signal based on the feedback loop.

Abstract: A communication device is provided that includes a modulation circuit configured to modulate a signal comprising a first signal portion of a first data type and a second signal portion of a second data type. The modulation circuit is configured to modulate the first signal portion in accordance with a first modulation scheme and the second signal portion in accordance with a second modulation scheme. At least one of the first data type is different from the second data type or the second modulation scheme is different from the first modulation scheme. The communication device further includes a modification circuit configured to modify the modulated first signal portion based on a first modification scheme and the second signal portion based on a second modification scheme. The communication device further includes a transmitter configured to transmit the modified first signal portion and the modified second signal portion.

Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.

Abstract: A wireless device and method of power consumption reduction are generally described herein. The wireless device may map a plurality of data symbols to sub-carriers for an orthogonal frequency division multiplexing (OFDM) transmission. The wireless device may divide the plurality of data symbols into first and second groups of data symbols. The wireless device may generate a first OFDM signal from the first group of data symbols for amplification by a first power amplifier (PA). The wireless device may generate a second OFDM signal from the second group of data symbols for amplification by a second PA. The data symbols of the first and second groups may be selected to provide a PAPR of the first OFDM signal that is lower than a PAPR of a composite OFDM signal based on the plurality of data symbols.

Abstract: A spur cancelation system includes error circuitry, inverse spur circuitry, and injection circuitry. The error circuitry is configured to generate an error signal based at least on a first transceiver signal in a transceiver signal processing chain. The inverse spur circuitry is configured to, based at least on the error signal, determine a gain and a phase of a spur signal in the transceiver signal and generate an inverse spur signal based at least on the gain and the phase of the spur signal. The injection circuitry is configured to inject the inverse spur signal to cancel a spur in a second transceiver signal in the transceiver signal processing chain.

Abstract: Systems, methods, and circuitries for synchronizing a first phase locked loop (PLL) with a second PLL are provided. In one example a PLL system includes a first PLL configured to generate a first signal; a second PLL configured to generate a second signal; and phase calculation circuitry. The phase calculation circuitry is configured to calculate a phase of the first signal at a given time; and provide the calculated phase to the second PLL for use by the second PLL in synchronizing a phase of the second with the phase of the first signal.

Abstract: The present disclosure relates to methods and apparatuses for compensating carrier or clock signal phase fluctuations. An apparatus comprises a digital phase locked loop (210) comprising a phase error output (214) for a phase error (216) between a reference signal (218) and an output signal (212) generated by the digital phase locked loop, and a phase rotator (220) coupled to the phase error output (214) and configured to rotate a phase of a data signal based on the phase error (216).

Abstract: A method for predistorting an input signal of an amplifier device comprises evaluating a selection criterion for a computational model of the amplifier device. The computational model provides an output signal of the amplifier device for the input signal of the amplifier device. Further, the method comprises selecting between a first computational model of the amplifier device and a second computational model of the amplifier device based on the evaluated selection criterion. Additionally, the method comprises predistorting the input signal of the amplifier device using the selected computational model.