Patents by Inventor Michael Konevecki
Michael Konevecki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9853090Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and methods of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. The gates overlie the global bit lines with one or more insulating layers therebetween to provide adequate isolation between the gates and the global bit lines. Processes for fabricating the vertical TFT select devices utilize a gate dielectric and optional dielectric bases to provide isolation between the gates and bit lines.Type: GrantFiled: December 15, 2016Date of Patent: December 26, 2017Assignee: SanDisk Technologies LLCInventors: Michael Konevecki, Steve Radigan, Vance Dunton, Natalie Nguyen, Luke Zhang
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Patent number: 9704920Abstract: A memory device includes at least one memory cell. The at least one memory cell includes a steering element, a resistive memory element, and a tunneling dielectric element located between the steering element and the resistive memory element.Type: GrantFiled: October 27, 2015Date of Patent: July 11, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Abhijit Bandyopadhyay, Venkatagirish Nagavarapu, Xiao Li, Zhida Lan, Michael Konevecki
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Publication number: 20170117324Abstract: A memory device includes at least one memory cell. The at least one memory cell includes a steering element, a resistive memory element, and a tunneling dielectric element located between the steering element and the resistive memory element.Type: ApplicationFiled: October 27, 2015Publication date: April 27, 2017Inventors: Abhijit BANDYOPADHYAY, Venkatagirish NAGAVARAPU, Xiao LI, Zhida LAN, Michael KONEVECKI
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Publication number: 20170098685Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and methods of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. The gates overlie the global bit lines with one or more insulating layers therebetween to provide adequate isolation between the gates and the global bit lines. Processes for fabricating the vertical TFT select devices utilize a gate dielectric and optional dielectric bases to provide isolation between the gates and bit lines.Type: ApplicationFiled: December 15, 2016Publication date: April 6, 2017Applicant: SanDisk Technologies LLCInventors: Michael Konevecki, Steve Radigan, Vance Dunton, Natalie Nguyen, Luke Zhang
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Patent number: 9558949Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and methods of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. The gates overlie the global bit lines with one or more insulating layers therebetween to provide adequate isolation between the gates and the global bit lines. Processes for fabricating the vertical TFT select devices utilize a gate dielectric and optional dielectric bases to provide isolation between the gates and bit lines.Type: GrantFiled: November 11, 2015Date of Patent: January 31, 2017Assignee: SanDisk Technologies LLCInventors: Michael Konevecki, Steve Radigan, Vance Dunton, Natalie Nguyen, Luke Zhang
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Publication number: 20160300885Abstract: A three-dimensional (3D) non-volatile memory array is provided having multiple word line layers stacked vertically with interleaving insulating layers over a vertically-oriented thin film transistor (TFT). The vertically-oriented TFT is used as a bit line selection device to couple a global bit line to a vertical bit line formed in a trench between portions of the word line and insulating layer stack. The word line layers are recessed horizontally to form recesses relative to the vertical bit line trench. The horizontal recesses provide spatial separation between memory cell areas and surfaces exposed during process steps. A memory material is formed conformally within the recesses, followed by a thin protective film. The film protects the memory material during etching to expose the vertical TFT for contact to the vertical bit line. Methods of fabricating arrays including recessed memory cell areas are provided.Type: ApplicationFiled: April 8, 2015Publication date: October 13, 2016Applicant: SanDisk 3D LLCInventors: Michael Konevecki, Vance Dunton, Steve Radigan
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Patent number: 9450023Abstract: A three-dimensional (3D) non-volatile memory array is provided having multiple word line layers stacked vertically with interleaving insulating layers over a vertically-oriented thin film transistor (TFT). The vertically-oriented TFT is used as a bit line selection device to couple a global bit line to a vertical bit line formed in a trench between portions of the word line and insulating layer stack. The word line layers are recessed horizontally to form recesses relative to the vertical bit line trench. The horizontal recesses provide spatial separation between memory cell areas and surfaces exposed during process steps. A memory material is formed conformally within the recesses, followed by a thin protective film. The film protects the memory material during etching to expose the vertical TFT for contact to the vertical bit line. Methods of fabricating arrays including recessed memory cell areas are provided.Type: GrantFiled: April 8, 2015Date of Patent: September 20, 2016Assignee: SanDisk Technologies LLCInventors: Michael Konevecki, Vance Dunton, Steve Radigan
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Publication number: 20160064222Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and methods of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. The gates overlie the global bit lines with one or more insulating layers therebetween to provide adequate isolation between the gates and the global bit lines. Processes for fabricating the vertical TFT select devices utilize a gate dielectric and optional dielectric bases to provide isolation between the gates and bit lines.Type: ApplicationFiled: November 11, 2015Publication date: March 3, 2016Applicant: SANDISK 3D LLCInventors: Michael Konevecki, Steve Radigan, Vance Dunton, Natalie Nguyen, Luke Zhang
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Patent number: 9202694Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and methods of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. The gates overlie the global bit lines with one or more insulating layers therebetween to provide adequate isolation between the gates and the global bit lines. Processes for fabricating the vertical TFT select devices utilize a gate dielectric and optional dielectric bases to provide isolation between the gates and bit lines.Type: GrantFiled: March 4, 2014Date of Patent: December 1, 2015Assignee: SanDisk 3D LLCInventors: Michael Konevecki, Steve Radigan, Vance Dunton, Natalie Nguyen, Luke Zhang
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Patent number: 8987119Abstract: A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer.Type: GrantFiled: February 14, 2011Date of Patent: March 24, 2015Assignee: Sandisk 3D LLCInventors: Vance Dunton, S. Brad Herner, Paul Wai Kie Poon, Chuanbin Pan, Michael Chan, Michael Konevecki, Usha Raghuram
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Publication number: 20140248763Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and methods of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. The gates overlie the global bit lines with one or more insulating layers therebetween to provide adequate isolation between the gates and the global bit lines. Processes for fabricating the vertical TFT select devices utilize a gate dielectric and optional dielectric bases to provide isolation between the gates and bit lines.Type: ApplicationFiled: March 4, 2014Publication date: September 4, 2014Applicant: SanDisk 3D LLCInventors: Michael Konevecki, Steve Radigan, Vance Dunton, Natalie Nguyen, Luke Zhang
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Patent number: 8445385Abstract: Memory cells, and methods of forming such memory cells are provided that include a steering element coupled to a carbon-based reversible resistivity-switching material. In particular embodiments, methods in accordance with this invention etch a carbon nano-tube (“CNT”) film formed over a substrate, the methods including coating the substrate with a masking layer, patterning the masking layer, and etching the CNT film through the patterned masking layer using a non-oxygen based chemistry. Other aspects are also described.Type: GrantFiled: April 10, 2009Date of Patent: May 21, 2013Assignee: SanDisk 3D LLCInventors: April D. Schricker, Andy Fu, Michael Konevecki, Steven Maxwell
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Patent number: 8329512Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.Type: GrantFiled: May 3, 2012Date of Patent: December 11, 2012Assignee: SanDisk 3D LLCInventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen, Raghuveer Makala, Vance Dunton
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Publication number: 20120276744Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.Type: ApplicationFiled: May 3, 2012Publication date: November 1, 2012Applicant: SanDisk 3D LLCInventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen, Raghuveer Makala, Vance Dunton
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Patent number: 8268678Abstract: A method of making a non-volatile memory device includes providing a substrate having a substrate surface, and forming a non-volatile memory array over the substrate surface. The non-volatile memory array includes an array of semiconductor diodes, and each semiconductor diode of the array of semiconductor diodes is disposed substantially parallel to the substrate surface.Type: GrantFiled: November 18, 2010Date of Patent: September 18, 2012Assignee: SanDisk 3D LLCInventors: Steven Maxwell, Michael Konevecki, Mark H. Clark, Usha Raghuram
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Patent number: 8241969Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.Type: GrantFiled: August 24, 2011Date of Patent: August 14, 2012Assignee: SanDisk 3D LLCInventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen, Raghuveer Makala, Vance Dunton
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Patent number: 8187932Abstract: A non-volatile memory device contains a three dimensional stack of horizontal diodes located in a trench in an insulating material, a plurality of storage elements, a plurality of word lines extending substantially vertically, and a plurality of bit lines. Each of the plurality of bit lines has a first portion that extends up along at least one side of the trench and a second portion that extends substantially horizontally through the three dimensional stack of the horizontal diodes. Each of the horizontal diodes is a steering element of a respective non-volatile memory cell of the non-volatile memory device, and each of the plurality of storage elements is located adjacent to a respective steering element.Type: GrantFiled: October 15, 2010Date of Patent: May 29, 2012Assignee: SanDisk 3D LLCInventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Raghuveer S. Makala
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Publication number: 20120091413Abstract: A non-volatile memory device contains a three dimensional stack of horizontal diodes located in a trench in an insulating material, a plurality of storage elements, a plurality of word lines extending substantially vertically, and a plurality of bit lines. Each of the plurality of bit lines has a first portion that extends up along at least one side of the trench and a second portion that extends substantially horizontally through the three dimensional stack of the horizontal diodes. Each of the horizontal diodes is a steering element of a respective non-volatile memory cell of the non-volatile memory device, and each of the plurality of storage elements is located adjacent to a respective steering element.Type: ApplicationFiled: October 15, 2010Publication date: April 19, 2012Applicant: SanDisk 3D LLCInventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Raghuveer S. Makala
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Publication number: 20110306174Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.Type: ApplicationFiled: August 24, 2011Publication date: December 15, 2011Inventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen, Raghuveer Makala, Vance Dunton
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Patent number: 8026178Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.Type: GrantFiled: January 12, 2010Date of Patent: September 27, 2011Assignee: SanDisk 3D LLCInventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Yung-Tin Chen, Raghuveer Makala, Vance Dunton