Abstract: A method and system for performing floating point additive arithmetic operations of long operands in a narrow dataflow. The operands include first and second floating point numbers having first and second mantissas, respectively, the second operand greater than the first operand. The mantissas are both separated into a low portion and a high portion, the high portions are loaded into N-bit operand registers. The high portion of the first mantissa is aligned with respect to the high portion of the second mantissa, the high portions are then moved into 2N-bit registers. The low portion of the first mantissa is aligned in accordance with the alignment of the first mantissa high portion. The low portions of both mantissas are then concatenated into the registers, the first mantissa concatenated using a hold-function circuit. A 2N-bit-wide adder performs the additive arithmetic operation on the concatenated mantissas.

Abstract: A system for performing floating point arithmetic operations including a plurality of stages making up a pipeline, the stages including a first stage and a last stage. The system also includes a register file adapted for receiving a store instruction for input to the pipeline, where the data associated with the store instruction is dependent on a previous operation still in the pipeline. The system further includes a store register adapted for outputting the data associated with the store instruction to memory and a control unit having instructions. The instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the last stage in the pipeline to the store register for use by the store instruction if the previous operation immediately precedes the store operation in the pipeline and if there is a data type match between the store instruction and the previous operation.

Abstract: A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes computer instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.

Abstract: A system for performing limited out-of order execution of floating point loads. The system includes a plurality of stages making up a pipeline, the stages including an early stage. The system also includes a mechanism for inputting an arithmetic instruction into the pipeline, the arithmetic instruction including a result address. The mechanism also determines if the arithmetic instruction causes a write after write (WAW) condition to occur before writing a result of the arithmetic instruction to the result address. The determining includes comparing the result address to a load address associated with a load instruction subsequent to the arithmetic instruction in the pipeline. The load data associated with the load instruction was written to the load address in the early stage of the pipeline. A WAW condition occurs if the result address is equal to the load address. Writing a result of the arithmetic instruction is suppressed in response to the WAW condition occurring.

Abstract: A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes a mechanism for performing a shift or masking operation in response to determining that the operand is in an un-normalized format. The system also includes instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.

Abstract: A system for performing floating point arithmetic operations including a plurality of stages making up a pipeline, the stages including a first stage and a last stage. The system also includes a register file adapted for receiving a store instruction for input to the pipeline, where the data associated with the store instruction is dependent on a previous operation still in the pipeline. The system further includes a store register adapted for outputting the data associated with the store instruction to memory and a control unit having instructions. The instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the last stage in the pipeline to the store register for use by the store instruction if the previous operation immediately precedes the store operation in the pipeline and if there is a data type match between the store instruction and the previous operation.

Abstract: A method and system for performing floating point additive arithmetic operations of long operands in a narrow dataflow. The operands include first and second floating point numbers having first and second mantissas, respectively, the second operand greater than the first operand. The mantissas are both separated into a low portion and a high portion, the high portions are loaded into N-bit operand registers. The high portion of the first mantissa is aligned with respect to the high portion of the second mantissa, the high portions are then moved into 2N-bit registers. The low portion of the first mantissa is aligned in accordance with the alignment of the first mantissa high portion. The low portions of both mantissas are then concatenated into the registers, the first mantissa concatenated using a hold-function circuit. A 2N-bit-wide adder performs the additive arithmetic operation on the concatenated mantissas.

Abstract: Arithmetic processing circuits in a circuit in a floating point processor having a fused multiply/ADD circuitry. In order to avoid waiting cycles in the normalizer of the floating point arithmetic, control logic calculates in an extremely early state of the overall Multiply/Add processing. Parts of the intermediate add result are significant and have to be selected in the pre-normalizer multiplexer to be fed to the normalizer by counting the leading zero bits (LZB) of the addend in a dedicated circuit right at the beginning of the pipe. LZB is added to the shift amount (SA) that is calculated to align the addend and is then compared with the width of the incrementer. If the sum of (SA+LZB) is larger than the width of the incrementer, which is a constant value, then no significant bits are in the high-part of the intermediate result, and the pre-normalizer multiplexer selects the data from a second predetermined position, otherwise from a first predetermined position.

Abstract: A process is provided for monitoring the conversion of numerical values from a first to a second format, where before and after the conversion, the modulo residue of the corresponding numerical value is calculated and compared with the corresponding residue after the conversion. In this way it is possible to effect error-free monitoring of such a conversion, especially of computer data, without great hardware expenditure.

Abstract: A method and system for use in a data processing system is proposed, wherein the Input Exponent is used already in the subblocks of the mantissa addition. Early in the flow of a cycle, there are parts of the Potential exponent result generated and put together using zero detect signals and carry select signals of the Carry Select Adder of the mantissa addition. For the addition of two floating point numbers this reduces the number of required logic gates in the timing critical path. This allows a faster cycle time and/or less latency and/or more complex functions. The method and system according to the invention can be applied to adders of different mantissa widths or different exponent widths as well as power of radix 2.

Abstract: Nitrile impurities are eliminated from polymers which contain acyclic N-vinyl-carboxamide and/or vinylamine units by treating the polymers with at least one oxidizing agent a) with exposure to light and/or b) in the presence of heavy metal ions.

Abstract: Copolymers which are obtained by copolymerization ofa) from 5 to 99 mol % of N-vinylcarboxamides,b) from 95 to 1 mol % of monoethylenically unsaturated carboxylic acids and/or the alkali metal, alkaline earth metal, ammonium or amine salts thereof, and if required,c) up to 30 mol % of other monoethylenically unsaturated compounds, and if required,d) up to 2 mol % of crosslinking agents,and subsequent partial or complete elimination of the acyl groups from the N-vinylcarboxamides polymerized in the copolymer, with formation of amino or ammonium groups, are used as additives to paper stock for increasing the drainage rate and the retention in papermaking, and the dry and wet strength of the paper.

Abstract: Abstract of the Disclosure: Insoluble, only slightly swellable polymers containing amino groups, which can be obtained from popcorn polymers containing units of the structure ##STR1## where R and R.sup.1 are H or C.sub.1 -C.sub.4 -alkyl, by eliminating the group R--CO-- from at least 2% of the incorporated units of the structure I, with the formation of units of the structure II ##STR2## a process for the preparation of the amino-containing popcorn polymers by polymerizing N-vinylcarboxamides and, if desired, other monoethylenically unsaturated monomers copolymerizable therewith with from 0.

Abstract: Graft polymers are obtainable by free radical polymerization of(A) monomers or monomer mixtures of(a) from 10 to 100% by weight of open-chain N-vinylcarboxamides(b) from 0 to 90% by weight of other, carboxyl-free monoethylenically unsaturated monomers which are copolymerizable with the monomers (a) and(c) from 0 to 5% by weight of monomers containing two or more ethylenically unsaturated, non-conjugated double bonds in the molecule,in the presence of(B) natural substances containing saccharide structures, such as mono-, oligo- and polysaccharides,in a weight ratio (A):(B) of from 95:5 to 20:80 and, if required, subsequent hydrolysis of the amido groups of the polymerized monomers (a) of the graft polymer with formation of amino groups, and said polymers are used as dry and wet strength agents for paper, board and cardboard.

Abstract: Cationic urea/formaldehyde resins are obtainable by condensing urea and formaldehyde in a molar ratio of from 1:1.5 to 1:3 in the presence of polymers which contain not less than 1 mol % of polymerized vinylamine units and have Fikentscher K values of from 5 to 300, in an amount of from 5 to 50 g per mole of urea in the end product, where the mixture is first a) precondensed at a pH of from 8 to 14, then acidified and b) condensed at a pH of from 1 to 5 until gel formation begins, c) then from 0.3 to 1.5 moles of formaldehyde are added per mole of urea used, d) post-condensation is carried out and e) the resin solution is subsequently neutralized. The resins thus obtained are used in papermaking as assistants for increasing the dry and wet strength of paper and result in less dulling of the whiteness of the paper.

Abstract: Graft polymers are obtainable by free radical polymerization of(A) monomers or monomer mixtures of(a) from 10 to 100% by weight of open-chain N-vinylcarboxamides(b) from 0 to 90% by weight of other, carboxyl-free moneothylenically unsaturated monomers which are copolymerizable with the monomers (a) and(c) from 0 to 5% by weight of monomers containing two or more ethylenically unsaturated, non-conjugated double bonds in the molecule,in the presence of(B) natural substances containing saccharide structures, such as mono-, oligo- and polysaccharides,in a weight ratio (A):(B) of from 95:5 to 20:80 and, if required, subsequent hydrolysis of the amido groups of the polymerized monomers (a) of the graft polymer with formation of amino groups, and said polymers are used as dry and wet strength agents for paper, board and cardboard.

Abstract: Cationic urea/formaldehyde resins are obtainable by condensing urea and formaldehyde in a molar ratio of from 1:1.5 to 1:3 in the presence of polymers which contain not less than 1 mol % of polymerized vinylamine units and have Fikentscher K values of from 5 to 300, in an amount of from 5 to 50 g per mole of urea in the end product, where the mixture is first a) precondensed at a pH of from 8 to 14, then acidified and b) condensed at a pH of from 1 to 5 until gel formation begins, c) then from 0.3 to 1.5 moles of formaldehyde are added per mole of urea used, d) post-condensation is carried out and e) the resin solution is subsequently neutralized. The resins thus obtained are used in papermaking as assistants for increasing the dry and wet strength of paper and result in less dulling of the whiteness of the paper.

Abstract: A process for the preparation of 4-substituted imidazoles of the general formula ##STR1## in which R denotes C.sub.1 -C.sub.20 alkyl, C.sub.3 -C.sub.20 cycloalkyl, aryl, and C.sub.7 -C.sub.20 aralkyl,whereina) N-formyl-.alpha.-aminonitriles of the general formula I ##STR2## in which R has the meanings stated above and A stands for carbonyl, are reacted, at a temperature ranging from 20.degree. to 200.degree. C. and a pressure ranging from 20 to 500 bar, with hydrogen in the presence of hydrogenation catalysts andb) the resulting N-formyl-1,2-diamines of the general formula ##STR3## in which R and A have the meanings stated above and n stands for 0 or 1, are reacted over a cyclization/dehydrogenation catalyst at a temperature ranging from 200.degree. to 600.degree. C. and a pressure ranging from 0.001 to 5 bar.

Abstract: Graft polymers are obtainable by free radical polymerization of(A) monomers or monomer mixtures of(a) from 10 to 100% by weight of open-chain N-vinylcarboxamides(b) from 0 to 90% by weight of other, carboxyl-free monoethylenically unsaturated monomers which are copolymerizable with the monomers (a) and(c) from 0 to 5% by weight of monomers containing two or more ethylenically unsaturated, non-conjugated double bonds in the molecule, in the presence of(B) natural substances containing saccharide structures, such as mono-, oligo- and polysaccharides,in a weight ratio (A):(B) of from 95:5 to 20:80 and, if required, subsequent hydrolysis of the amido groups of the polymerized monomers (a) of the graft polymer with formation of amino groups, and said polymers are used as dry and wet strength agents for paper, board and cardboard.

Abstract: A method of stabilizing N-vinylformamide, which may contain customary polymerization inhibitors, against polymerization during storage or transport, comprises adding to the N-vinylformamide monomers of the general formula ##STR1## where R+H, CH.sub.3 ##STR2## R.sup.2 +C.sub.1 -C.sub.4 -alkyl, as stabilizer in amounts of from 1 to 99 .degree.6 by weight, based on the mixture.