Abstract: A circuit support structure includes a first metal layer, a second metal layer, isolation material containing the first and second metal layers, an isolation circuit, a first plurality of contact pads, and a second plurality of contact pads. The isolation circuit includes a first circuit element in the first metal layer and a second circuit element in the second metal layer and electrically isolated from the first circuit element by the isolation material. The first plurality of contact pads is adapted to be coupled to a first integrated circuit on the circuit support structure and includes a first contact pad electrically coupled to the first circuit element. The second plurality of contact pads is adapted to be coupled to a second integrated circuit on the circuit support structure and includes a second contact pad electrically coupled to the second circuit element.

Abstract: A system includes a high side transistor switch coupled to a first voltage node and a low side transistor switch coupled to the high side transistor switch at a switch node. The system further includes a unidirectional decoupling capacitor circuit including a capacitive component. The unidirectional decoupling capacitor circuit is coupled between the first voltage node and a common potential. Responsive to a voltage on the first voltage node being more than a threshold greater than an input voltage to the first voltage node, the unidirectional decoupling capacitor circuit is configured to sink current from the first voltage node to the capacitive component. The capacitive component can therefore be charged, with the charge used to subsequently power a load.

Abstract: Methods, apparatus, and systems are disclosed to drive a transistor. An example apparatus includes a regulator including a first input terminal adapted to be coupled to a control terminal of a transistor, a first output terminal, and a second output terminal, a first stage including a first input terminal coupled to the first output terminal of the regulator and an output terminal adapted to be coupled to the control terminal of the transistor, and a second stage including an input terminal coupled to the second output terminal of the regulator, and an output terminal adapted to be coupled to the control terminal of the transistor.

Abstract: A startup circuit includes an enhancement mode transistor with a drain coupled to a startup circuit input, a source coupled to a first node, and a gate coupled to a second node. The startup circuit includes a current limiting circuit that controls a current path between the second node and a startup circuit output node based on a current sense voltage signal representing a current through the enhancement mode transistor, and a voltage regulation circuit controls a voltage of the second node to regulate a startup circuit output voltage of the startup circuit output node.

Abstract: In some examples, a system comprises a bi-directional gallium nitride (GaN) device including first and second switches and a substrate, the first switch including a first gate and a first source, the second switch including a second gate and a second source, and the substrate shared between the first and second switches. The system include a third switch coupled to the first source and the substrate. The system includes a fourth switch coupled to the second source and the substrate and a comparator having inputs coupled to the first and second sources and outputs coupled to the third and fourth switches.

Abstract: Gate drivers and auto-zero comparators are disclosed. An example integrated circuit includes a transistor comprising a gate terminal and a current terminal, a gallium nitride (GaN) gate driver coupled to the gate terminal, the GaN gate driver configured to adjust operation of the transistor, and an enhancement mode GaN comparator coupled to at least one of the transistor the GaN gate driver, the enhancement mode GaN comparator configured to compare a voltage to a reference voltage, the voltage based on current from the current terminal, the GaN gate driver configured to adjust the operation of the transistor based on the comparison.

Abstract: Disclosed examples include inverting buck-boost DC-DC converter circuits with a switching circuit to alternate between first and second buck mode phases for buck operation in a first mode, including connecting an inductor and a capacitor in series between an input node and a reference node to charge the inductor and the capacitor in the first buck mode phase, and connecting the inductor and the capacitor in parallel between an output node and the reference node to discharge the inductor and the capacitor to the output node.

Abstract: A startup circuit includes an enhancement mode transistor with a drain coupled to a startup circuit input, a source coupled to a first node, and a gate coupled to a second node. The startup circuit includes a current limiting circuit that controls a current path between the second node and a startup circuit output node based on a current sense voltage signal representing a current through the enhancement mode transistor, and a voltage regulation circuit controls a voltage of the second node to regulate a startup circuit output voltage of the startup circuit output node.

Abstract: Methods, systems, and apparatus to facilitate high side control of a switching power converter are disclosed. An example apparatus includes a latch including a first node coupled to a first source of a first switch and an output coupled to a first gate of the first switch; a first diode coupled to the first node and a second node; a second diode coupled to the second node and ground; a second switch coupled to a voltage source and the second node; and a third switch including a third gate coupled to the second switch, a third source coupled to the second node, and a third drain coupled to the latch.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for cross-conduction detection. An example apparatus includes a cross detector circuit including a first transistor and a second transistor, the first transistor coupled to a load, a third transistor coupled to a first controlled delay circuit and the first transistor, a fourth transistor coupled to a second controlled delay circuit and to the third transistor at a phase node, and a control circuit coupled to the first controlled delay circuit, the second controlled delay circuit, and the load.

Abstract: Methods, systems, and apparatus to facilitate high side control of a switching power converter are disclosed. An example apparatus includes a latch including a first node coupled to a first source of a first switch and an output coupled to a first gate of the first switch; a first diode coupled to the first node and a second node; a second diode coupled to the second node and ground; a second switch coupled to a voltage source and the second node; and a third switch including a third gate coupled to the second switch, a third source coupled to the second node, and a third drain coupled to the latch.

Abstract: Methods, systems, and apparatus to facilitate high side control of a switching power converter are disclosed. An example apparatus includes a latch including a first node coupled to a first source of a first switch and an output coupled to a first gate of the first switch; a first diode coupled to the first node and a second node; a second diode coupled to the second node and ground; a second switch coupled to a voltage source and the second node; and a third switch including a third gate coupled to the second switch, a third source coupled to the second node, and a third drain coupled to the latch.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for cross-conduction detection. An example apparatus includes a cross detector circuit including a first transistor and a second transistor, the first transistor coupled to a load, a third transistor coupled to a first controlled delay circuit and the first transistor, a fourth transistor coupled to a second controlled delay circuit and to the third transistor at a phase node, and a control circuit coupled to the first controlled delay circuit, the second controlled delay circuit, and the load.

Abstract: Methods, systems, and apparatus to facilitate high side control of a switching power converter are disclosed. An example apparatus includes a latch including a first node coupled to a first source of a first switch and an output coupled to a first gate of the first switch; a first diode coupled to the first node and a second node; a second diode coupled to the second node and ground; a second switch coupled to a voltage source and the second node; and a third switch including a third gate coupled to the second switch, a third source coupled to the second node, and a third drain coupled to the latch.

Abstract: Described examples include DC to DC converters and systems with switching circuitry formed by four series-connected switches, inductors connected between the ends of the switching circuitry and corresponding output nodes, and with a flying capacitor coupled across interior switches of the switching circuitry and a second capacitor coupled across the ends of the switching circuitry. A control circuit operates the switching circuit to control a voltage signal across the output nodes using a first clock signal and a phase shifted second clock signal to reduce output ripple current and enhance converter efficiency using valley current control. The output inductors are wound on a common core in certain examples.

Abstract: In some examples, a system comprises a bi-directional gallium nitride (GaN) device including first and second switches and a substrate, the first switch including a first gate and a first source, the second switch including a second gate and a second source, and the substrate shared between the first and second switches. The system include a third switch coupled to the first source and the substrate. The system includes a fourth switch coupled to the second source and the substrate and a comparator having inputs coupled to the first and second sources and outputs coupled to the third and fourth switches.

Abstract: Disclosed examples include inverting buck-boost DC-DC converter circuits with a switching circuit to alternate between first and second buck mode phases for buck operation in a first mode, including connecting an inductor and a capacitor in series between an input node and a reference node to charge the inductor and the capacitor in the first buck mode phase, and connecting the inductor and the capacitor in parallel between an output node and the reference node to discharge the inductor and the capacitor to the output node.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for cross-conduction detection. An example apparatus includes a cross detector circuit including a first transistor and a second transistor, the first transistor coupled to a load, a third transistor coupled to a first controlled delay circuit and the first transistor, a fourth transistor coupled to a second controlled delay circuit and to the third transistor at a phase node, and a control circuit coupled to the first controlled delay circuit, the second controlled delay circuit, and the load.

Abstract: A system includes a high side transistor switch coupled to a first voltage node and a low side transistor switch coupled to the high side transistor switch at a switch node. The system further includes a unidirectional decoupling capacitor circuit including a capacitive component. The unidirectional decoupling capacitor circuit is coupled between the first voltage node and a common potential. Responsive to a voltage on the first voltage node being more than a threshold greater than an input voltage to the first voltage node, the unidirectional decoupling capacitor circuit is configured to sink current from the first voltage node to the capacitive component. The capacitive component can therefore be charged, with the charge used to subsequently power a load.

Abstract: A controller for a DC-DC converter includes a state machine and a plurality of drivers for controlling switches in the DC-DC converter, where each state in the state machine determines a state of the drivers, and a plurality of timers, where each state in the state machine, other than a passive state, has an associated timer for the state of the drivers.