Abstract: A method of producing an apparatus comprising an electrical circuit that has one or more characteristics that meet a design specification is presented. The method includes designing the electrical circuit with a trim circuit having a trim value that is variable, The electrical circuit is adjustable based on the trim value of the trim circuit. There is encoding of the functional circuit information and/or trim circuit information in a tag, The method has a reading of the functional circuit information and/or the trim circuit information stored in the tag and the determining of the trim value for the trim circuit that results in the characteristic of the electrical circuit meeting the design specification using the functional circuit information and/or the trim circuit information.

Abstract: An interface for communicating between two device is provided that includes an interface input for receiving an input signal as well as a comparator circuit coupled to the interface input. The comparator circuit is adapted to provide a clock signal and a data signal based on the input signal to a first memory device having a first input for receiving the data signal and a second input for receiving the clock signal.

Abstract: An interface for communicating between two device is provided that includes an interface input for receiving an input signal as well as a comparator circuit coupled to the interface input. The comparator circuit is adapted to provide a clock signal and a data signal based on the input signal to a first memory device having a first input for receiving the data signal and a second input for receiving the clock signal.

Abstract: A method and apparatus for adaptive test time reduction is provided. The method begins with running a predetermined number of structural tests on wafers or electronic chips. Pass/fail data is collected once the predetermined number of structural tests have been run. This pass/fail data is then used to determine which of the predetermined number of structural tests are consistently passed. The consistently passed tests are then grouped into slices within the test vectors. Once the grouping has been performed, the consistently passed tests are skipped when testing future production lots of the wafers or electronic chips. A sampling rate may be modulated if it is determined that adjustments in the tests performed are needed. In addition, a complement of the tests performed on the wafers may be performed on the electronic chips to ensure complete test coverage.

Abstract: A wrapper for automatic test pattern generation uses the functional bus when testing cores on an integrated circuit device. The functional bus is between the bus wrapper and the cores. During normal operation, the functional bus operates as a standard bus to communicate functional inputs and outputs between the cores and in/out of the integrated circuit device. During test operation, test signals are communicated on the functional bus. As a result, each core does not require its own wrapper; this allows the bus wrapper to reduce the area occupied by test circuitry.

Abstract: An Automated Test Equipment (ATE) system is configured to test a Device Under Test (DUT). The ATE system stores a Procedure Description Language program. The ATE system interprets the program, thereby causing a configured scan path to be set up in the DUT and causing bit values to be loaded into that scan path. During testing, it is sometimes desirable to change only bit values in certain scan path bit locations. In a data recirculation operation, the ATE system shifts bit values, on a bit-by-bit basis, out of the configured scan path via the TDO terminal of the DUT and shifts back in either the shifted out bit value or a replacement bit value. The shift back into the configured scan path occurs via the TDI terminal of the DUT so that each bit value in the scan path is replaced with its previous value or a replacement value.

Abstract: In one configuration, the method for verifying a test vector includes simulating a pattern on a netlist of the IC and selecting at least one path in the netlist of the IC based on a result of the simulation. The method further includes generating timing information of the at least one path and storing the timing information of the at least one path. In another configuration, the apparatus for verifying a test vector of the (IC) includes a memory and at least one processor coupled to the memory. The at least one processor is configured to simulate a pattern on a netlist of the IC, to select at least one path in the netlist of the IC based on a result of the simulation, to generate timing information of the at least one path, and to store the timing information of the at least one path.

Abstract: An integrated circuit product package configured to continuity testing is described. The integrated circuit product package includes a package substrate. The package substrate includes internal routing connections. The integrated circuit product package also includes a semiconductor die coupled to the package substrate. The semiconductor die includes input/output (I/O) pins and switches. The switches selectively coupled the I/O pins to facilitate a daisy chain connection. The daisy chain connection includes circuitry fabricated on the semiconductor die, more than two of the internal routing connections, more than two of the I/O pins and at least one switch.

Abstract: An integrated circuit product package configured to continuity testing is described. The integrated circuit product package includes a package substrate. The package substrate includes internal routing connections. The integrated circuit product package also includes a semiconductor die coupled to the package substrate. The semiconductor die includes input/output (I/O) pins and switches. The switches selectively coupled the I/O pins to facilitate a daisy chain connection. The daisy chain connection includes circuitry fabricated on the semiconductor die, more than two of the internal routing connections, more than two of the I/O pins and at least one switch.

Abstract: A first apparatus, such as a die or a semiconductor package, has signal paths extending through the apparatus. The signal paths can include through vias and other components. The signal paths are operable to communicate with a second apparatus when the second apparatus is stacked with the first apparatus. The first apparatus also has pass gates. Each pass gate is configurable in response to a signal, to short a pair of the signal paths to enable substantially simultaneous testing of the signal paths. The pass gates may be configurable to isolate the signal paths during operation of the first apparatus.

Abstract: A semiconductor die includes a group of spacer cells within the semiconductor die. The spacer cells include fiducial markings therein. The fiducial markings can be located within a metal layer, a diffusion layer, a polysilicon layer, and/or a Shallow Trench Isolation (STI) structure.

Abstract: An integrated circuit, or combination of integrated circuits, has a primary interconnect, a redundant interconnect, and circuitry connecting the primary and redundant interconnects allowing selection of the redundant interconnect to bypass the primary interconnect.

Abstract: An integrated circuit configured for testing is described. The integrated circuit includes a high-speed input/output interface. The integrated circuit also includes a test controller coupled to the high-speed input/output interface. The integrated circuit further includes test circuitry coupled to the test controller. The test controller controls the test circuitry based on controller protocol test information from the high-speed input/output interface.

Abstract: Defect prediction information is determined for a segment of an integrated circuit layout. Marker information is obtained, for example from user input into a computer design tool, where the marker information defines the segment. A segment can be defined to be any arbitrary portion of the layout and can include portions of multiple blocks. The marker information is used to extract layout information corresponding to the segment. The extracted segment layout information is analyzed to determine the defect prediction information. In one example, the determination involves performing a Critical Area Analysis such that the defect prediction information is a yield prediction value. This process is repeated for multiple segments, and the defect prediction information for the segments is compared to identify the segment most susceptible to defects. The user can modify the design of the segment, and repeat the process to improve yield in the manufacture of the integrated circuit.

Abstract: Quiescent supply current (IDDQ) verification, prediction, and debugging of low power semiconductor devices are enhanced by IDDQ defect diagnosis. If all IDDQ patterns fail verification, per module analysis is performed to sort out potential module design issues or cell constraint issues. For issues of missing constraints, and cell design or implementation issues leading to extra leakage that could be avoided by adding constraints, there are usually IDDQ patterns that correlate with expectations, and patterns that do not, due to the random nature of unconstrained scan cell values as determined by the pattern generation tool. Differentiating good and bad IDDQ patterns can identify root causes of IDDQ issues and additional constraints to fix the bad IDDQ vectors. These verification procedures are achieving IDDQ test success and short time to market, as well as significantly faster time to volume and improved yields because of having a higher quality and better-controlled IDDQ test.

Abstract: Techniques for designing and storing test input and output data vectors to diagnose bit errors in a testing sequence. In an aspect, test input vectors may be chosen such that the corresponding correct output vectors form codewords of a forward error-correcting code. In another aspect, the correct test output vectors may be compressed to reduce the memory requirements of the testing system. In yet another aspect, test input vectors may be sorted such that the test output vectors are monotonically increasing or decreasing in sequence, and corresponding delta's between output vectors in the sequence may be stored to reduce the memory requirements. Further aspects provide for storing information relating to the correct output vectors in various efficient formats, including storing base value-referenced offsets, and storing relative operations and output vector segments to allow derivation of correct output vectors from memory when required.

Abstract: Procedures are disclosed to automate constraint and power mode (PM) setup determination for quiescent power supply current (IDDQ) testing of a semiconductor design. Starting with known constraints and PM setup, if available, an estimation is run to obtain minimum, lower bound (LB), expected, upper bound (UB), and maximum IDDQ estimates for individual cells. The estimates are sorted by range (UB-LB), and by elevation (expected-minimum). A constraint is added to control the power of the cell with the highest range. A constraint or a PM entry is added to reduce elevation of the cell with the highest elevation, based on a predetermined property of the cell. With the adjusted constraints and PM setup, the steps are repeated. Iteration continues until (1) the top cells are not custom cells, memories, or macros, or (2) the contributions of the top cells to the design's range and elevation are below predetermined limits.

Abstract: An Automated Test Equipment (ATE) system is configured to test a Device Under Test (DUT). The ATE system stores a Procedure Description Language program. The ATE system interprets the program, thereby causing a configured scan path to be set up in the DUT and causing bit values to be loaded into that scan path. During testing, it is sometimes desirable to change only bit values in certain scan path bit locations. In a data recirculation operation, the ATE system shifts bit values, on a bit-by-bit basis, out of the configured scan path via the TDO terminal of the DUT and shifts back in either the shifted out bit value or a replacement bit value. The shift back into the configured scan path occurs via the TDI terminal of the DUT so that each bit value in the scan path is replaced with its previous value or a replacement value.

Abstract: A semiconductor die includes a group of spacer cells within the semiconductor die. The spacer cells include fiducial markings therein. The fiducial markings can be located within a metal layer, a diffusion layer, a polysilicon layer, and/or a Shallow Trench Isolation (STI) structure.

Abstract: An integrated circuit that supports testing of multiple pads via a subset of these pads includes at least two sections. Each section has multiple pads and multiple test access circuits coupled to these pads. For each section, one pad is designated as a primary pad and the remaining pads are designated as secondary pads. For each section, the test access circuits couple the secondary pads to the primary pad such that all of the pads in the section can be tested by probing just the primary pad. Each test access circuit may be implemented with a simple switch. A controller generates a set of control signals for the test access circuits in all sections. These control signals enable and disable the test access circuits such that all of the sections can be tested in parallel, and the pads in each section can be tested in a sequential order.