Patents by Inventor Michael Lowe
Michael Lowe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230174008Abstract: Refrigeration units for cooling the interior of a trailer or vehicle, related software, systems and methods for deploying and managing such units. The refrigeration unit comprises a refrigeration system configured to mount to the trailer or vehicle. The refrigeration unit further comprises a battery rack configured to receive at least one of a plurality of rechargeable batteries so as to allow it to be swapped into and out of the rack to provide adaptive battery capacity. A power management system is configured to receive DC power from the plural batteries and deliver power to a compressor of the refrigeration system. A controller is configured to control the refrigeration system to cool the interior to a predetermined temperature.Type: ApplicationFiled: May 14, 2021Publication date: June 8, 2023Applicant: SUNSWAP LTDInventors: Michael Lowe, Andrew Sucis, Nikolai Tauber
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Patent number: 11668833Abstract: Virtual bumpers for autonomous vehicles improve effectiveness and safety as such vehicles are operated. One or more sensor systems having a Lidar sensor and a camera sensor determine proximity of objects around the vehicle and facilitate identification of the environment around the vehicle. The sensor systems are placed at various locations around the vehicle. The vehicle identifies an object and one or more properties of the identified object using the sensor systems. Based on the identified object and the properties of the object, a virtual bumper may be created for that object. For example, if the object is identified as another vehicle moving with a certain velocity, the vehicle may determine a minimum space to avoid the other vehicle, either by changing direction or reducing the velocity of the vehicle, with the minimum space constituting a virtual bumper.Type: GrantFiled: November 3, 2021Date of Patent: June 6, 2023Assignee: CYNGN, INC.Inventors: Michael Lowe, Ain McKendrick, Andrea Mariotti, Pranav Bajoria, Biao Ma
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Patent number: 11640837Abstract: A method used in forming a memory array comprises forming digitlines above and electrically couple to memory cells there-below. The digitlines are laterally-spaced relative one another in a vertical cross-section. An upwardly-open void-space is laterally-between immediately-adjacent of the digitlines in the vertical cross-section. Conductive material of the digitlines is covered with masking material that is in and less-than-fills the upwardly-open void-spaces. The masking material is removed from being directly above tops of the digitlines to expose the conductive digitline material and to leave the masking material over sidewalls of the conductive digitline material in the upwardly-open void-spaces. Insulative material is selectively grown from the exposed conductive digitline material relative to the masking material across the upwardly-open void-spaces to form covered void-spaces there-from between the immediately-adjacent digitlines in the vertical cross-section.Type: GrantFiled: August 9, 2021Date of Patent: May 2, 2023Assignee: Micron Technology, Inc.Inventors: Armin Saeedi Vahdat, Richard J. Hill, Aaron Michael Lowe
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Patent number: 11527623Abstract: Some embodiments include an integrated transistor having an active region comprising semiconductor material. The active region includes a first source/drain region, a second source/drain region and a channel region between the first and second source/drain regions. A conductive gating structure is operatively proximate the channel region and comprises molybdenum. The integrated transistor may be incorporated into integrated memory, such as, for example, DRAM, FeFET memory, etc. Some embodiments include methods of forming integrated assemblies and devices, such as, for example, integrated transistors, integrated memory, etc.Type: GrantFiled: July 28, 2020Date of Patent: December 13, 2022Assignee: Micron Technology, Inc.Inventor: Aaron Michael Lowe
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Publication number: 20220352324Abstract: Some embodiments include an integrated transistor having an active region comprising semiconductor material. The active region includes a first source/drain region, a second source/drain region and a channel region between the first and second source/drain regions. A conductive gating structure is operatively proximate the channel region and comprises molybdenum. The integrated transistor may be incorporated into integrated memory, such as, for example, DRAM, FeFET memory, etc. Some embodiments include methods of forming integrated assemblies and devices, such as, for example, integrated transistors, integrated memory, etc.Type: ApplicationFiled: July 18, 2022Publication date: November 3, 2022Applicant: Micron Technology, Inc.Inventor: Aaron Michael Lowe
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Publication number: 20220351464Abstract: This specification describes systems and methods for refining point cloud data. Methods can include receiving point cloud data for a physical space, iteratively selecting points along an x, y, and z dimension, clustering the selected points into 2D histograms, determining a slope value for each 2D histogram, and removing, based on the slope value exceeding a predetermined value, points from the point cloud data. Methods can also include iteratively voxelizing each 2D histogram into predetermined mesh sizes, summating points in each voxelized 2D histogram, removing, based on determining the summation is below a predetermined sum value, points from the point cloud data, keeping, based on determining that a number of points in each voxelized 2D histogram exceeds a threshold value, a center point, selecting, for each histogram, a point, identifying, nearest neighbors in the point cloud data, removing the identified nearest neighbors from the data, and returning remaining points.Type: ApplicationFiled: July 11, 2022Publication date: November 3, 2022Inventors: Christopher Frank Eckman, Brady Michael Lowe, Alexander Hall
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Publication number: 20220335688Abstract: This specification describes systems and methods for generating a mapping of a physical space from point cloud data for the physical space. The methods can include receiving the point cloud data for the physical space, filtering the point cloud data to, at least, remove sparse points from the point cloud data, aligning the point cloud data along x, y, and z dimensions that correspond to an orientation of the physical space, and classifying the points in the point cloud data as corresponding to one or more types of physical surfaces. The methods can also include identifying specific physical structures in the physical space based, at least in part, on classifications for the points in the point cloud data, and generating the mapping of the physical space to identify the specific physical structures and corresponding contours for the specific physical structures within the orientation of the physical space.Type: ApplicationFiled: April 14, 2021Publication date: October 20, 2022Inventors: Christopher Frank Eckman, Brady Michael Lowe
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Publication number: 20220310637Abstract: Some embodiments include an integrated transistor having an active region comprising semiconductor material. A conductive gating structure is adjacent to the active region. The conductive gating structure includes an inner region proximate the active region and includes an outer region distal from the active region. The inner region includes a first material containing titanium and nitrogen, and the outer region includes a metal-containing second material. The second material has a higher conductivity than the first material. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: March 29, 2021Publication date: September 29, 2022Applicant: Micron Technology, Inc.Inventors: Aaron Michael Lowe, Zhuo Chen, Marko Milojevic, Timothy A. Quick, Richard J. Hill, Scott E. Sills
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Publication number: 20220296957Abstract: A wearable resistance apparatus includes a waist band and a pair of leg resistance assemblies. Each leg resistance assembly includes a leg anchor, a foot anchor and at least one resistance band. The resistance bands preferably attach between a waist area and a foot area of a wearer and each extend down a rear of the wearer's legs. When the resistance bands are moved into a resistant position, tension is created in lower body muscles of the wearer, such as gluteal muscles, hamstring muscles and/or calf muscles. The wearable resistance apparatus provides exercise to the wearer during everyday activities and also provides enhanced exercise when performing activities such as walking, cycling, jogging and running.Type: ApplicationFiled: March 10, 2022Publication date: September 22, 2022Inventors: Dalton Harold Von Hagen, Hayden Michael Lowes
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Patent number: 11403817Abstract: This specification describes systems and methods for refining point cloud data. Methods can include receiving point cloud data for a physical space, iteratively selecting points along an x, y, and z dimension, clustering the selected points into 2D histograms, determining a slope value for each 2D histogram, and removing, based on the slope value exceeding a predetermined value, points from the point cloud data. Methods can also include iteratively voxelizing each 2D histogram into predetermined mesh sizes, summating points in each voxelized 2D histogram, removing, based on determining the summation is below a predetermined sum value, points from the point cloud data, keeping, based on determining that a number of points in each voxelized 2D histogram exceeds a threshold value, a center point, selecting, for each histogram, a point, identifying, nearest neighbors in the point cloud data, removing the identified nearest neighbors from the data, and returning remaining points.Type: GrantFiled: April 14, 2021Date of Patent: August 2, 2022Assignee: Lineage Logistics, LLCInventors: Christopher Frank Eckman, Brady Michael Lowe, Alexander Hall
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Publication number: 20220183416Abstract: A chin strap assembly comprises a chin cup and a chin strap for mounting the chin cup to a helmet. The chin cup has a first side for contacting a user's chin and a second side opposite the first side, the second side including a first engaging structure. The chin strap has a second engaging structure for coupling the chin strap to the chin cup via the first engaging structure. The first engaging structure is offset on the chin cup and the second engaging structure is offset on the chin strap to provide various positioning options of the chin cup relative to the helmet.Type: ApplicationFiled: December 1, 2021Publication date: June 16, 2022Inventors: Michael Lowe, Whitman Kwok
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Patent number: 11275401Abstract: Various implementations described herein are directed to a device having alarm circuitry that receives a clock signal and provides alarm chain signals based on the clock signal. The device may include delay chain circuitry that receives the alarm chain signals from the alarm circuitry and provides delay chain signals. The device may include output circuitry that receives the delay chain signals from the delay chain circuitry and provides an alarm control signal based on the delay chain signals.Type: GrantFiled: January 15, 2020Date of Patent: March 15, 2022Assignee: Arm LimitedInventor: Ivan Michael Lowe
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Publication number: 20220059693Abstract: Some embodiments include an integrated assembly having an access device between a storage element and a conductive structure. The access device has channel material which includes semiconductor material. The channel material has a first end and an opposing second end, and has a side extending from the first end to the second end. The first end is adjacent the conductive structure, and the second end is adjacent the storage element. Conductive gate material is adjacent the side of the channel material. A first domed metal-containing cap is over the conductive structure and under the channel material and/or a second domed metal-containing cap is over the channel material and under the storage element. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: August 20, 2020Publication date: February 24, 2022Applicant: Micron Technology, Inc.Inventors: Yoshitaka Nakamura, Yi Fang Lee, Jerome A. Imonigie, Scott E. Sills, Aaron Michael Lowe
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Publication number: 20220037483Abstract: Some embodiments include an integrated transistor having an active region comprising semiconductor material. The active region includes a first source/drain region, a second source/drain region and a channel region between the first and second source/drain regions. A conductive gating structure is operatively proximate the channel region and comprises molybdenum. The integrated transistor may be incorporated into integrated memory, such as, for example, DRAM, FeFET memory, etc. Some embodiments include methods of forming integrated assemblies and devices, such as, for example, integrated transistors, integrated memory, etc.Type: ApplicationFiled: July 28, 2020Publication date: February 3, 2022Applicant: Micron Technology, Inc.Inventor: Aaron Michael Lowe
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Publication number: 20220022589Abstract: A helmet includes a helmet body and a clip coupled to the helmet body, for retaining a helmet accessory such as a face cage. The clip comprises a first clip section partly defining an aperture into which a part of the helmet accessory can be received and a second clip section located opposite the first clip section. The second clip section has a first end and a second end, the first end partly defining the aperture into which the part of the helmet accessory can be received, and the second end being coupled to the helmet body. The second clip section further includes a ramped surface that can be depressed to provide access to or from the aperture by the part of the helmet accessory. Also disclosed is a clip for retaining a helmet accessory.Type: ApplicationFiled: July 23, 2021Publication date: January 27, 2022Inventors: Michael Lowe, Whitman Kwok, David Stoutamire
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Patent number: 11205776Abstract: A method for forming lithium metal oxides comprised of Ni, Mn and Co useful for making lithium ion batteries comprises providing precursor particulates of Ni and Co that are of a particular size that allows the formation of improved lithium metal oxides. The method allows the formation of lithium metal oxides having improved safety while retaining good capacity and rate capability. In particular, the method allows for the formation of lithium metal oxide where the primary particle surface Mn/Ni ratio is greater than the bulk Mn/Ni. Likewise the method allows the formation of lithium metal oxides with secondary particles having much higher densities allowing for higher cathode densities and battery capacities while retaining good capacity and rate performance.Type: GrantFiled: May 14, 2015Date of Patent: December 21, 2021Assignee: Dow Global Technologies LLCInventors: Yu-Hua Kao, Murali G. Theivanayagam, Jui-Ching Lin, Jianxin Ma, Liang Chen, Michael Lowe, Hideaki Maeda, Ing-Feng Hu
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Patent number: 11195378Abstract: A computer-implemented method of operating a regulated gaming machine may comprise accepting, in the regulated gaming machine, funds from a player and enabling the player to play a wager-based game having a plurality of stages and enabling, for a game session, game play and wagers at a current stage of the game. A determination may then be made whether game play has reached a stage complete state in which all requirements necessary for transitioning game play to a next or another stage of the plurality of stages, as may be a determination whether this is a first time, during the game session, that the game play has reached the stage complete state for the current stage. An incentive may be offered to the player to transition game play to the next or another stage when game play has reached the stage complete state for the first time and not offering the player the incentive otherwise.Type: GrantFiled: July 20, 2020Date of Patent: December 7, 2021Assignee: SYNERGY BLUE LLCInventors: Michael Oberberger, Michael Low
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Publication number: 20210366525Abstract: A method used in forming a memory array comprises forming digitlines above and electrically couple to memory cells there-below. The digitlines are laterally-spaced relative one another in a vertical cross-section. An upwardly-open void-space is laterally-between immediately-adjacent of the digitlines in the vertical cross-section. Conductive material of the digitlines is covered with masking material that is in and less-than-fills the upwardly-open void-spaces. The masking material is removed from being directly above tops of the digitlines to expose the conductive digitline material and to leave the masking material over sidewalls of the conductive digitline material in the upwardly-open void-spaces. Insulative material is selectively grown from the exposed conductive digitline material relative to the masking material across the upwardly-open void-spaces to form covered void-spaces there-from between the immediately-adjacent digitlines in the vertical cross-section.Type: ApplicationFiled: August 9, 2021Publication date: November 25, 2021Applicant: Micron Technology, Inc.Inventors: Armin Saeedi Vahdat, Richard J. Hill, Aaron Michael Lowe
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Patent number: 11169271Abstract: Virtual bumpers for autonomous vehicles improve effectiveness and safety as such vehicles are operated. One or more sensor systems having a Lidar sensor and a camera sensor determine proximity of objects around the vehicle and facilitate identification of the environment around the vehicle. The sensor systems are placed at various locations around the vehicle. The vehicle identifies an object and one or more properties of the identified object using the sensor systems. Based on the identified object and the properties of the object, a virtual bumper may be created for that object. For example, if the object is identified as another vehicle moving with a certain velocity, the vehicle may determine a minimum space to avoid the other vehicle, either by changing direction or reducing the velocity of the vehicle, with the minimum space constituting a virtual bumper.Type: GrantFiled: September 20, 2019Date of Patent: November 9, 2021Assignee: CYNGN, INC.Inventors: Michael Lowe, Ain Mckendrick, Andrea Mariotti, Pranav Bajoria, Biao Ma
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Patent number: 11120852Abstract: A method used in forming a memory array comprises forming digitlines above and electrically couple to memory cells there-below. The digitlines are laterally-spaced relative one another in a vertical cross-section. An upwardly-open void-space is laterally-between immediately-adjacent of the digitlines in the vertical cross-section. Conductive material of the digitlines is covered with masking material that is in and less-than-fills the upwardly-open void-spaces. The masking material is removed from being directly above tops of the digitlines to expose the conductive digitline material and to leave the masking material over sidewalls of the conductive digitline material in the upwardly-open void-spaces. Insulative material is selectively grown from the exposed conductive digitline material relative to the masking material across the upwardly-open void-spaces to form covered void-spaces there-from between the immediately-adjacent digitlines in the vertical cross-section.Type: GrantFiled: February 18, 2020Date of Patent: September 14, 2021Assignee: Micron Technology, Inc.Inventors: Armin Saeedi Vahdat, Richard J. Hill, Aaron Michael Lowe