Abstract: An overcap structure supports an electronic tag on a container cap. The overcap structure includes an overcap for supporting the electronic tag where the overcap is rotatably positionable about the cap of the container. The overcap includes a planar upper surface and depending annular skirt having an inwardly directed lip for positioning beneath the cap. The overcap is formed of mating components which are attachable about the cap preventing nondestructible detachment of the overcap from the container cap.

Abstract: The present invention provides for an electronic tag housing used to support electronic tags to an article with a shrink wrap tube. The present invention provides an electronic tag assembly, including a housing, having a base and a cover attachable to the base. The housing includes a cavity for supporting an electronic tag. A heat shrinkable tube is supported by the housing between the cover and attachable base.

Abstract: A system and method for an efficient implementation of a software-managed cache is presented. When an application thread executes on a simple processor, the application thread uses a conditional data select instruction for eliminating a conditional branch instruction when accessing a software-managed cache. An application thread issues a conditional data select instruction (DMA transfer) after a cache directory lookup, wherein the size of the requested data is dependent upon the outcome of the cache directory lookup. When the cache directory lookup results in a cache hit, the application thread requests a transfer of zero bits of data, which results in a DMA controller (DMAC) performing a no-op instruction. When the cache directory lookup results in a cache miss, the application thread requests a data block transfer the size of a corresponding cache line.

Abstract: Loading software on a plurality of processors is presented. A processing unit (PU) retrieves a file from system memory and loads it into its internal memory. The PU extracts a processor type from the file's header which identifies whether the file should execute on the PU or a synergistic processing unit (SPU). If an SPU should execute the file, the PU DMA's the file to the SPU for execution. In one embodiment, the file is a combined file which includes both PU and SPU code. In this embodiment, the PU identifies one or more section headers included in the file which indicates embedded SPU code within the combined file. In this embodiment, the PU extracts the SPU code from the combined file and DMA's the extracted code to an SPU for execution.

Abstract: A housing assembly supports an electronic tag to the extending neck of a bottle. The housing assembly includes a housing for accommodating the electronic tag. The housing has an annular bearing surface for engagement with the extending neck of the bottle. A strap is coupled to the housing about the bottle neck. The strap has a bearing surface for engagement with the extending neck where the bearing surface of the strap is tapered to match the taper of the extending neck of the bottle.

Abstract: The present invention provides a method and apparatus for creating memory barriers in a Direct Memory Access (DMA) device. A memory barrier command is received and a memory command is received. The memory command is executed based on the memory barrier command. A bus operation is initiated based on the memory barrier command. A bus operation acknowledgment is received based on the bus operation. The memory barrier command is executed based on the bus operation acknowledgment. In a particular aspect, memory barrier commands are direct memory access sync (dmasync) and direct memory access enforce in-order execution of input/output (dmaeieio) commands.

Abstract: A component of a microprocessor-based data processing system, which includes features for regulating power consumption in snoopable components and has gating off memory coherency properties, is determined to be in a relatively inactive state and is transitioned to a non-snoopable low power mode. Then, when a snoop request occurs, a retry protocol is sent in response to the snoop request. In conjunction with the retry protocol, a signal is sent to bring the component into snoopable mode. When the retry snoop is requested, the component is in full power mode and can properly respond to the snoop request. After the snoop request has been satisfied, the component again enters into a low power mode.

Abstract: A boot is positionable about a rotatable wheel having an axle extending therefrom. A pair of mating components include interconnecting elements for attaching the elements about the wheel preventing non-destructible detachment of the mating components. Flanges extend from the mating components to prevent attempts to rotate the boot about the wheel. The flanges which support the interconnecting elements are frangibly removable from the body to permit destructible detachment of the mating components from the wheel. The boot may support an electronic tag such as radio frequency identification (RFID) tag or an electronic article surveillance (EAS) tag.

Abstract: Methods and apparatus provide for transferring a plurality of data blocks between a shared memory and a local memory of a processor in response to a single DMA command issued by the processor to a direct memory access controller (DMAC), wherein the processor is capable of operative communication with the shared memory and the DMAC is operatively coupled to the local memory.

Abstract: A device supports an electronic tag to extending neck of a bottle where the extending neck includes a perimetrical undercut thereabout. The device includes a housing formed of a pair of matable housing portions for attachment about the neck of the bottle. At least one of the housing portions supports an electronic tag. A rim is formed on each housing portion. The rim portions are mutually engageable and align to form a perimetrical rim. The perimetrical rim of the housing is seatable in the undercut of the neck to prevent longitudinal movement of the mated housing portions along the neck.

Abstract: The present invention provides for an apparatus employed to debug a program operating in a supplemental processor when the processor's registers are not readable directly by the debugging operation of a main processor. A program operating in main memory halts due to operational errors. The program code lines save to a cache. In the main processor, a pool of memory is reserved. A copy of the data from the nominally inaccessible supplementary processor registers also transfers to the reserved storage area for processing of the program needing debugging. After the program debugging is complete, a copy of the contents of the memory pool is restored to the memory of the target supplemental processor. A copy of the local store register state and remaining local store data returns to main memory.

Abstract: Disclosed herein is a security hang tag that includes a body, a head and a strap. The body includes a head-receiving compartment defining a circumferentially-extending flange. The head includes a circumferentially-extending lip to engage the flange, capturing the lip within the compartment such that the head is rotatably secured to the body. The head has a first strap-receiving channel including a first locking shoulder and a second strap-receiving channel including a second locking shoulder. The strap has first and second ends and includes a first cavity at the first end and a second cavity at the second end. The first end is configured for insertion within the first strap-receiving channel until the first cavity engages the first locking shoulder and the second end is configured for insertion within the second strap-receiving channel until the second cavity engages the second locking shoulder.

Abstract: An electronic tag housing which may be secured to variously configured containers, such as containers having curved surfaces. The housing could have a base and a cover overlying the base for support of a tag therebetween. A flexible suction cup is secured to the base, the suction cup has an upper surface and an opposed lower suction surface for suction attachment to the article surface. An adhesive is applied to the lower suction surface for additional attachment to the suction cup to the curved surface.

Abstract: Grouping processors is presented. A processing unit (PU) initiates an application and identifies the application's requirements. The PU assigns one or more synergistic processing units (SPUs) and a memory space to the application in the form of a group. The application specifies whether the task requires shared memory or private memory. Shared memory is a memory space that is accessible by the SPUs and the PU. Private memory, however, is a memory space that is only accessible by the SPUs that are included in the group. When the application executes, the resources within the group are allocated to the application's execution thread. Each group has its own group properties, such as address space, policies (i.e. real-time, FIFO, run-to-completion, etc.) and priority (i.e. low or high). These group properties are used during thread execution to determine which groups take precedence over other tasks.

Abstract: The present invention provides a mechanism for a processor to write data to a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. The locking cache or other fast memory can be used as additional system memory. In an embodiment of the invention, the locking cache is one or more sets of ways, but not all of the sets or ways, of a multiple set associative cache.

Abstract: The present invention provides a mechanism of storing data transferred from an I/O device, a network, or a disk into a portion of a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. In an embodiment of the invention, a processor can write data to the cache or other fast memory without also writing it to main memory. The portion of the cache or other fast memory can be used as additional system memory.

Abstract: To alleviate at least some of the costs associated with context switching, addition fields, either with associated Application Program Interfaces (APIs) or coupled to application modules, can be employed to indicate points of light weight context during the operation of an application. Therefore, an operating system can pre-empt applications at points where the context is relatively light, reducing the costs on both storage and bus usage.

Abstract: The present invention provides for a system comprising a DMA queue configured to receive a DMA command comprising a tag, wherein the tag belongs to one of a plurality of tag groups. A counter couples to the DMA queue and is configured to increment a tag group count of the tag group to which the tag belongs upon receipt of the DMA command by the DMA queue and to decrement the tag group count upon execution of the DMA command. A tag group count status register couples to the counter and is configured to store the tag group count for each of the plurality of tag groups. And the tag group count status register is further configured to receive a request for a tag group status and to respond to the request for the tag group status.

Abstract: An adjustable bracket for supporting a first building member extending in a first direction relative to a second building member extending in a second direction, the bracket including a pair of bracket portions, each bracket portion having an attachment flange oriented in a first plane, a side support oriented in a second plane and a base wall oriented in a third plane, wherein the separation distance between the side supports of the respective bracket portions is adjustable to accommodate different thickness of first building members therebetween.

Abstract: A method and apparatus are provided for efficiently managing limited resources is a given computer system. The system utilizes a token manager that assigns tokens to groups of associated requestors. The tokens are then utilized by the requesters to occupy the given resource. The allocation of these tokens, thus, prevents such problems as denial of service due to a lack of available resources.