Abstract: The subject technology can be embodied in an earpiece that includes a body, a retaining structure, and a movable joint structure. The body includes an acoustic passage for conducting sound waves. The retaining structure is configured to engage with external structural features to hold the body in position, and the movable joint structure is configured to couple the body to the retaining structure. The movable joint structure is also configured to allow angular motion of the body with respect to the retaining structure.

Abstract: A memory macro includes a plurality of columns and a plurality of switching circuits. A column of the plurality of columns has a plurality of voltage supply nodes corresponding to a plurality of memory cells in the column. A switching circuit of the plurality of switching circuits corresponds to a column of the plurality of columns and is configured to selectively provide a first voltage value of a first voltage source or a second voltage value of a second voltage source to the voltage supply nodes. The first voltage value and the second voltage value differ by a predetermined voltage value.

Abstract: Provided herein are compounds, compositions and methods for balancing a T-helper cell profile and in particular Th1, Th2, Th17 and Treg cell profiles, and related methods and compositions for treating or preventing an inflammatory condition associated with an imbalance of a T-helper cell profile.

Abstract: Provided herein are compounds, compositions and methods for balancing a T-helper cell profile and in particular Th1, Th2, Th17 and Treg cell profiles, and related methods and compositions for treating or preventing an inflammatory condition associated with an imbalance of a T-helper cell profile.

Abstract: A computer system may access data corresponding to a portfolio that comprises interest rate swaps and may calculate parameters for a compressed swap. The computer system may determine, based at least in part on the parameters for the compressed swap, a performance bond requirement attributable to the interest rate swaps. The computer system may compare the performance bond requirement to account data associated with a holder of the portfolio and may perform one or more additional actions based on the comparing.

Abstract: Provided are peptide analogues of PA-IL and compositions containing them. The PA-IL peptide analogues have altered carbohydrate binding specificity relative to a PA-IL of SEQ ID NO:1, and thus the analogues contain amino acid substitutions in SEQ ID NO:1. The substitutions can be at positions 50, 52 and 53 of SEQ ID NO:1 and can include combinations of amino acid substitutions at those positions. Also included are methods for detecting changes in the glycosylation of carbohydrates and for separating biomolecules which contain glycoproteins or glycoconjugates.

Abstract: A self-repair unit includes a self-repair address comparator configured to receive address information from a control logic circuit, and to compare the received address with a faulty address in a memory array. The self-repair unit further includes a redundant engine configured to re-direct access to a redundancy address in a redundant memory if the received address matches the faulty address, wherein the redundancy address corresponds to the faulty address in the memory array. The self-repair unit further includes a cache stack counter configured to determine a number of pending repairs in a corrected data cache connected to the memory array and to the redundant memory.

Abstract: A polymer membrane is formed around nanotubes by applying either droplets or a thin film of a suspension of the nanotubes over a layer of a solution of the polymer, the suspending medium for the nanotubes and the solvent(s) for the polymer selected such that the suspending agent will evaporate while it is migrating into and dispersing in the solvent. When the polymer is then permitted to coagulate around the nanotubes, the coagulated polymer will fix the orientations of the nanotubes and a high proportion of the nanotubes will protrude from both sides of the resulting membrane to provide through-passages through the membrane.

Abstract: Provided are peptide analogs of PA-IL and compositions containing them. The PA-IL peptide analogs have altered carbohydrate binding specificity relative to a PA-IL of SEQ ID NO:1, and thus the analogs contain amino acid substitutions in SEQ ID NO:1. The substitutions can be at positions 50, 52 and 53 of SEQ ID NO:1 and can include combinations of amino acid substitutions at those positions. Also included are methods for detecting changes in the glycosylation of carbohydrates and for separating biomolecules which contain glycoproteins or glycoconjugates.

Abstract: A memory array has a plurality of rows including a plurality of memory words. Each first bit of a plurality of first bits is associated with a memory word of the each row. A state of the each first bit indicates whether the associated memory word has had an error. Each redundancy row of a plurality of redundancy rows includes a plurality of redundancy words. Each redundancy word is associated with a memory word. A corrected data cache has at least one repair word configured to store corrected data and at least one status bit associated with the at least one repair word, the status bit indicating whether the corrected data stored in the repair word is a pending repair. The corrected data cache is configured to write the corrected data stored in the repair word to at least one of a counterpart memory word or a counterpart redundancy word.

Abstract: A circuit includes a first memory cell and a data control circuit configured to provide first data and second data. The first memory cell has a first port and a second port. The first data is written from the first port to the first memory cell. The second data is based on information of the first data. The second port is configured to write the second data to the first memory cell based on a detection of a write disturb caused by the second port to the first port.

Abstract: A device layout tool includes a gate electrode layer, wherein the gate electrode layer is configured to define a three dimensional gate structure over a fin structure, wherein the fin structure has three exposed surfaces. The device layout tool further includes a defect-describing layer, wherein the defect-describing layer is configured to define locations of gate defects relative to the three exposed surfaces of the fin structure.

Abstract: A sense amplifier comprises a cross coupled pair of inverters, a first transistor, a second transistor, and a capacitive device. The cross coupled pair of inverters includes a first end, a second end, and a third end. The first end is configured to receive a first supply voltage. The second end is coupled with a first terminal of the capacitive device and a first terminal of the first transistor. The third end is coupled with a second terminal of the capacitive device and a first terminal of the second transistor. A second terminal of the first transistor and a second terminal of the second transistor are coupled together and are configured to receive a first control signal. A third terminal of the first transistor and a third terminal of the second transistor are coupled together and are configured to receive a second supply voltage different from the first supply voltage.

Abstract: A bonded, direct fixation fastener as supportive structure for a rail on a railroad tie or bed comprising: a rail plate, wherein the rail plate has a generally horizontal center portion having a lower face and an upper face and defining a rail plate horizontal plane, and wherein the rail plate center portion extends at a first angle from opposing sides as rail plate tongues above the rail plate horizontal plane, the rail plate having a rail securing device; a bed plate comprising a generally horizontal center portion, an upper bed plate face defining a bed plate horizontal plane, and a pair of opposing bed plate tongues extending from opposing sides of the bed plate horizontal center portion disposed at a second angle above the bed plate horizontal plane; a horizontal elastomeric portion of relatively lower durometer hardness encapsulating at least a portion of the bed plate and at least a portion of the rail plate; and vertical elastomeric portions of relatively higher durometer hardness encapsulating at lea

Abstract: An assembly to hold a rail boot to a rail during embedded track construction comprising: a cover having a bottom surface, a first portion of the bottom surface generally conforming to a length of a top surface of a rail head; the bottom surface having a second portion defining a convex shape adjacent to and generally parallel to the length of the top surface of the rail head; the bottom surface further defining a hook to engage a gauge side of the rail boot; and a clip having first and second ends, wherein the first end engages a gauge side of the cover; and the second end engages a field side of the cover and/or the rail boot.

Abstract: A bonded fastener for a railway rail comprising: top and bottom generally horizontal plates bonded and separated by an insulating material wherein the top plate defines a rail bed; a plurality of clip housings wherein each clip housing houses part of a hold-down clip for attaching the rail to the bonded fastener; a plurality of anchor assembly areas wherein each anchor assembly area defines an opening through the bonded fastener for receiving an attachment device for attaching the fastener to a supporting surface; and one or more generally vertical barriers comprising part of the bonded fastener. Further, a first generally horizontal barrier may extend from the bonded fastener underneath each of the clip housings, and a second generally horizontal barrier may extend from the rail bed underneath the rail on each side of the bonded fastener.

Abstract: Defect-describing (or “cut”) layer(s) for describing defects associated with different sides of a 3-dimensional (3D) structure enable fault modeling to determine the effect of position and location of defects on transistor performance. One or more defect-describing layers are used to identify the coordinates and sides of the 3D structures of the defects. The defect-describing layer(s) enables fault-modeling for 3D structures to understand the effects of faults on different locations, especially for defects associated with the fins of the finFET devices. Faults are injected to different locations and sides of fins and are modeled with different test vectors, test parameters and testing devices to identify detectable faults. The fault modeling would help identify the sources of defects and also improve layout design of finFET device structures.

Abstract: A sense amplifier includes a first transistor. The first transistor includes a gate connected to a bit line, and a first source/drain (S/D) electrically coupled with a global bit line. The sense amplifier further includes a second transistor. The second transistor includes a gate connected to a first signal line, and a first S/D coupled to the global bit line, wherein the second transistor is configured to pre-charge the bit line.

Abstract: A memory structure includes a memory row of a memory array, a plurality of first bits, a first redundancy row, and a plurality of second bits. The memory row includes a plurality of memory words. The plurality of first bits is configured to indicate whether an individual memory word of the plurality of memory words of the memory row has an error. The first redundancy row includes a plurality of first redundancy words. The plurality of second bits is configured to indicate whether an individual first redundancy word of the plurality of first redundancy words of the first redundancy row has an error.