Abstract: A belt fitting for a safety belt device, having a base section and a latch plate projecting from same. The base section has a belt eyelet with a belt strap running surface, which is in sliding contact with a belt strap guided through the belt eyelet when the safety belt is being worn, wherein, in the transverse direction of the belt strap, the belt strap running surface transitions on both sides at lateral corner regions into a belt eyelet edge opposite the belt strap running surface. The belt strap running surface has a surface contour which provides stable transverse guidance of the belt strap in the belt eyelet under loading conditions, which counteracts a transverse load component acting on the belt strap. A displacement body is formed on the belt eyelet edge-opposite the belt strap running surface, which reduces a gap width of the belt eyelet.

Abstract: A method for producing a model mould core blank uses a ceramic blank fixed to a processing holder. During fixing, a lost core is manufactured from the ceramic blank based on a CNC manufacturing process 3D model, the processing holder being fastened in the running CNC machine. A model blank is produced by casting model material around the lost core while fixing persists. The model blank becomes part of another method for producing a model mould core, wherein an outer contour of a lost model is produced from and/or on the model blank on the basis of a second CNC manufacturing process 3D model, wherein fixing and processing holder fastening also occurs. Another method produces a precision casting mould, in which a ceramic mould is applied to the outer contour of the lost model, and a cast part having a hollow cavity structure is produced by the precision casting mould.

Abstract: A belt fitting for a safety belt device, having a base section and a latch plate projecting from same. The base section has a belt eyelet with a belt strap running surface, which is in sliding contact with a belt strap guided through the belt eyelet when the safety belt is being worn, wherein, in the transverse direction of the belt strap, the belt strap running surface transitions on both sides at lateral corner regions into a belt eyelet edge opposite the belt strap running surface. The belt strap running surface has a surface contour which provides stable transverse guidance of the belt strap in the belt eyelet under loading conditions, which counteracts a transverse load component acting on the belt strap. A displacement body is formed on the belt eyelet edge-opposite the belt strap running surface, which reduces a gap width of the belt eyelet.

Abstract: Techniques and solutions are described for analyzing data collections to determine if they may be anomalous as compared with other data collections. For example, one or more values for data elements of a data collection may be unusually high or low, or may represent infrequently occurring values. Or, values of data elements in a data collection may not be anomalous when considered individually, but may be anomalous in combination. A machine learning model is trained with training data collections, where the training data collections include a plurality of data elements. An inference data collection, also having the data elements of the training data collections, is analyzed using the trained machine learning model to provide an anomaly score. The anomaly score can be based at least in part on feature anomaly scores, which indicate anomality of individual data elements of the inference data collection.

Abstract: A method for producing a model mould core blank uses a ceramic blank fixed to a processing holder. During fixing, a lost core is manufactured from the ceramic blank based on a CNC manufacturing process 3D model, the processing holder being fastened in the running CNC machine. A model blank is produced by casting model material around the lost core while fixing persists. The model blank becomes part of another method for producing a model mould core, wherein an outer contour of a lost model is produced from and/or on the model blank on the basis of a second CNC manufacturing process 3D model, wherein fixing and processing holder fastening also occurs. Another method produces a precision casting mould, in which a ceramic mould is applied to the outer contour of the lost model, and a cast part having a hollow cavity structure is produced by the precision casting mould.

Abstract: Some embodiments include reception of a time-series of a respective data value generated by each of a plurality of sensors, calculation of a regression associated with a first sensor of the plurality of sensors based on the received plurality of time-series, the regression being a function of the respective data values of the others of the plurality of data sources, reception of respective data values associated with a time from and generated by each the plurality of respective sensors, determination of a predicted value associated with the time for the first sensor based on the regression associated with the first sensor and on the respective data values associated with the time, comparison of the predicted value with the received value associated with the time and generated by the first sensor, and determination of a value indicating a likelihood of an anomaly based on the comparison.

Abstract: Some embodiments include reception of a time-series of a respective data value generated by each of a plurality of sensors, calculation of a regression associated with a first sensor of the plurality of sensors based on the received plurality of time-series, the regression being a function of the respective data values of the others of the plurality of data sources, reception of respective data values associated with a time from and generated by each the plurality of respective sensors, determination of a predicted value associated with the time for the first sensor based on the regression associated with the first sensor and on the respective data values associated with the time, comparison of the predicted value with the received value associated with the time and generated by the first sensor, and determination of a value indicating a likelihood of an anomaly based on the comparison.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to back gate tuning circuits and methods of manufacture. The method includes applying a voltage to a back gate of a device; and selectively controlling the applied voltage to deactivate at least one trap within an insulating layer of the device to reduce noise contribution from the at least one trap.

Abstract: Some embodiments include reception of a time-series of a respective data value generated by each of a plurality of sensors, calculation of a regression associated with a first sensor of the plurality of sensors based on the received plurality of time-series, the regression being a function of the respective data values of the others of the plurality of data sources, reception of respective data values associated with a time from and generated by each the plurality of respective sensors, determination of a predicted value associated with the time for the first sensor based on the regression associated with the first sensor and on the respective data values associated with the time, comparison of the predicted value with the received value associated with the time and generated by the first sensor, and determination of a value indicating a likelihood of an anomaly based on the comparison.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to back gate tuning circuits and methods of manufacture. The method includes applying a voltage to a back gate of a device; and selectively controlling the applied voltage to deactivate at least one trap within an insulating layer of the device to reduce noise contribution from the at least one trap.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to circuits with logical back-gate switching and methods of operation. The circuit includes at least one front-gate contact and digital back-gate potentials for logical function implementation on a back side of at least one device. The digital back-gate potentials are switchable between two logic levels.

Abstract: Some embodiments include reception of a time-series of a respective data value generated by each of a plurality of sensors, calculation of a regression associated with a first sensor of the plurality of sensors based on the received plurality of time-series, the regression being a function of the respective data values of the others of the plurality of data sources, reception of respective data values associated with a time from and generated by each the plurality of respective sensors, determination of a predicted value associated with the time for the first sensor based on the regression associated with the first sensor and on the respective data values associated with the time, comparison of the predicted value with the received value associated with the time and generated by the first sensor, and determination of a value indicating a likelihood of an anomaly based on the comparison.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to circuits with logical back-gate switching and methods of operation. The circuit includes at least one front-gate contact and digital back-gate potentials for logical function implementation on a back side of at least one device. The digital back-gate potentials are switchable between two logic levels.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to circuits with logical back-gate switching and methods of operation. The circuit includes at least one front-gate contact and digital back-gate potentials for logical function implementation on a back side of at least one device. The digital back-gate potentials are switchable between two logic levels.

Abstract: A device including a plurality of static random-access memory (SRAM) bitcells arranged in rows and columns, wherein the SRAM bitcells comprise fully depleted silicon-on-insulator field effect transistors (FDSOI-FETs). The FDSOI-FETs comprise P-channel-pull-up-transistors, wherein each P-channel-pull-up-transistor comprises a back gate. The device further includes a plurality of bitlines, wherein each bitline is electrically connected to the SRAM bitcells of one of the columns and a plurality of wordlines, wherein each wordline is electrically connected to the SRAM bitcells of one of the rows. The device further includes a bitline control circuit configured to select at least one column for writing, wherein during a write operation a first control signal is applied to the back gates of the P-channel-pull-up-transistors of the at least one column selected for writing and a second control signal to the back gates of the P-channel-pull-up-transistors of the columns not selected for writing.

Abstract: A device including a plurality of static random-access memory (SRAM) bitcells arranged in rows and columns, wherein the SRAM bitcells comprise fully depleted silicon-on-insulator field effect transistors (FDSOI-FETs). The FDSOI-FETs comprise P-channel-pull-up-transistors, wherein each P-channel-pull-up-transistor comprises a back gate. The device further includes a plurality of bitlines, wherein each bitline is electrically connected to the SRAM bitcells of one of the columns and a plurality of wordlines, wherein each wordline is electrically connected to the SRAM bitcells of one of the rows. The device further includes a bitline control circuit configured to select at least one column for writing, wherein during a write operation a first control signal is applied to the back gates of the P-channel-pull-up-transistors of the at least one column selected for writing and a second control signal to the back gates of the P-channel-pull-up-transistors of the columns not selected for writing.

Abstract: A memory array assembly and a method for performing a write operation without disturbing data stored in other SRAM cells are provided. The memory array assembly comprises a plurality of SRAM cells, a plurality of avoid-disturb cells, a plurality of sense amplifiers and a plurality of write drivers. The SRAM cells are arranged in rows and columns, wherein each column is coupled to an avoid-disturb cell, a sense amplifier, and a write driver. The avoid-disturb cell receives a select signal capable of assuming first or second states. An output of the sense amplifier is coupled to an input of the write driver when the select signal is in the first state. A data-in bus is coupled to the input of the write driver if the select signal is in the second state. The write driver then sends the output signal to the SRAM cell.

Abstract: A device includes an array of a plurality of memory cells, at least one N-well contact area and at least one P-well contact area. The memory cells are arranged in a plurality of rows and a plurality of columns. Each column includes an N-well region and at least one P-well region. The N-well and P-well regions extend between a first end of the column and a second end of the column. Each N-well contact area electrically contacts at least one of the N-well regions, wherein the N-well region of at least one of the columns is electrically contacted at only one of the first and second ends of the column. Each P-well contact area electrically contacts at least one of the P-well regions, wherein the P-well region of at least one of the columns is electrically contacted at only one of the first and second ends of the column.

Abstract: Immunogenic compositions and methods for eliciting an immune response against S. epidermidis and other related staphylococci are provided. The immunogenic compositions can include immunogenic conjugates of poly-?-glutamic acid (such as ?DLPGA) polypeptides of S. epidermidis, or related staphylococci that express a ?PGA polypeptide. The ?PGA conjugates elicit an effective immune response against S. epidermidis, or other staphylococci, in subjects to which the conjugates are administered. A method of treating an infection caused by a Staphylococcus organism that expresses cap genes is also disclosed. The method can include selecting a subject who is at risk of or has been diagnosed with the infection by the Staphylococcus organism which expresses ?PGA from the cap genes. Further, the expression of a ?PGA polypeptide by the organism can then be altered.

Abstract: A device includes an array of a plurality of memory cells, at least one N-well contact area and at least one P-well contact area. The memory cells are arranged in a plurality of rows and a plurality of columns. Each column includes an N-well region and at least one P-well region. The N-well and P-well regions extend between a first end of the column and a second end of the column. Each N-well contact area electrically contacts at least one of the N-well regions, wherein the N-well region of at least one of the columns is electrically contacted at only one of the first and second ends of the column. Each P-well contact area electrically contacts at least one of the P-well regions, wherein the P-well region of at least one of the columns is electrically contacted at only one of the first and second ends of the column.