Abstract: Methods for preparing a silicon oxynitride layer where the silicon oxynitride layer is deposited atop a substrate and have a low concentration of nitrogen at the interface of the silicon oxynitride layer and the substrate. The silicon oxynitride layer is formed by pulsing at least one interface precursor onto a substrate, where said substrate chemisorbs a portion of said at least one interface precursor to form a monolayer of said at least one interface precursor; and pulsing a nitrogen-containing precursor onto said substrate containing said monolayer of interface precursor, where said monolayer of said at least one interface precursor chemisorbs a portion of said nitrogen-containing precursor to form a monolayer of said nitrogen-containing precursor. The interface precursor includes oxygen-containing or silicon-containing precursor gasses.

Abstract: A 3D microelectronic structure is provided which includes a substrate having at least one opening present therein, the at least one opening having sidewalls which extend to a common bottom wall; and a thermal nitride layer present on at least an upper portion of each sidewall of openings. A method for fabricating the above-mentioned 3D microelectronic structure is also provided. Specifically, the method includes a step of selectively forming a thermal nitride layer on at least an upper portion of each sidewall of an opening formed in a substrate.

Abstract: A semiconductor device is fabricated using a micro-masking structure. The micro-masking structure is formed along the sidewalls of a trench in a semiconductor substrate or along the sidewalls of an electrode disposed over the semiconductor substrate. The micro-masking structure exposes portions of the sidewalls and covers other portions of the sidewalls. Then the exposed portions of the sidewalls are recessed to form a plurality of recesses such that the sidewalls have an increase surface area. After the recessing, the micro-masking structure is removed. The recessed sidewalls provide enhanced capacitance.

Abstract: A memory cell includes: a trench capacitor, including a trench silicon layer having an upper portion and a lower portion, and a buried plate disposed adjacent the lower portion of the trench silicon layer; an array FET having a gate portion, a drain portion, a source portion, and a buried strap coupled to one of the source and drain portions, the buried strap being in communication with the upper portion of the trench silicon layer; and a collar disposed about the upper portion of the trench silicon layer and between the buried strap and the buried plate, the collar including a re-entrant bend that is operable to decrease an electric field between the buried strap and the buried plate.

Abstract: A semiconductor device is fabricated using a micro-masking structure. The micro-masking structure is formed along the sidewalls of a trench in a semiconductor substrate or along the sidewalls of an electrode disposed over the semiconductor substrate. The micro-masking structure exposes portions of the sidewalls and covers other portions of the sidewalls. Then the exposed portions of the sidewalls are recessed to form a plurality of recesses such that the sidewalls have an increase surface area. After the recessing, the micro-masking structure is removed. The recessed sidewalls provide enhanced capacitance.

Abstract: A memory cell includes: a trench capacitor, including a trench silicon layer having an upper portion and a lower portion, and a buried plate disposed adjacent the lower portion of the trench silicon layer; an array FET having a gate portion, a drain portion, a source portion, and a buried strap coupled to one of the source and drain portions, the buried strap being in communication with the upper portion of the trench silicon layer; and a collar disposed about the upper portion of the trench silicon layer and between the buried strap and the buried plate, the collar including a re-entrant bend that is operable to decrease an electric field between the buried strap and the buried plate.

Abstract: Disclosed herein is a method, in an integrated, of forming a high-K node dielectric of a trench capacitor and a trench sidewall device dielectric at the same time. The method includes forming a trench in a single crystal layer of a semiconductor substrate, and forming an isolation collar along a portion of the trench sidewall, wherein the collar has a top below the top of the trench in the single crystal layer. Then, at the same time, a high-K dielectric is formed along the trench sidewall, the high-K dielectric extending in both an upper portion of the trench including above the isolation collar and in a lower portion of the trench below the isolation collar.

Abstract: A method and structure for an integrated circuit structure that includes introducing precursors on a substrate, oxidizing the precursors and heating the precursors. The introducing and the oxidizing of the precursors is preformed in a manner so as to form an amorphous glass dielectric on the substrate. The process preferably includes, before introducing the precursors on the substrate, cleaning the substrate.

Abstract: A 3D microelectronic structure is provided which includes a substrate having at least one opening present therein, the at least one opening having sidewalls which extend to a common bottom wall; and a thermal nitride layer present on at least an upper portion of each sidewall of openings. A method for fabricating the above-mentioned 3D microelectronic structure is also provided. Specifically, the method includes a step of selectively forming a thermal nitride layer on at least an upper portion of each sidewall of an opening formed in a substrate.

Abstract: A method and structure for an integrated circuit structure that includes introducing precursors on a substrate, oxidizing the precursors and heating the precursors. The introducing and the oxidizing of the precursors is preformed in a manner so as to form an amorphous glass dielectric on the substrate. The process preferably includes, before introducing the precursors on the substrate, cleaning the substrate. The introducing of precursors is performed in molar ratios consistent with formation of glass films and may comprise an atomic level chemical vapor deposition of La2O3 and Al2O3 using ratios between 20%-50% La2O3 and 50%-80% Al2O3.

Abstract: A 3D microelectronic structure is provided which includes a substrate having at least one opening present therein, the at least one opening having sidewalls which extend to a common bottom wall; and a thermal nitride layer present on at least an upper portion of each sidewall of openings. A method for fabricating the above-mentioned 3D microelectronic structure is also provided. Specifically, the method includes a step of selectively forming a thermal nitride layer on at least an upper portion of each sidewall of an opening formed in a substrate.

Abstract: Methods forming a trench region of a trench capacitor structure having increase surface area are provided. One method includes the steps of forming a discontinuous polysilicon layer on exposed walls of a lower trench region, the discontinuous polysilicon layer having gaps therein which expose portions of said substrate; oxidizing the lower trench region such that the exposed portions of said substrate provided by the gaps in the discontinuous polysilicon layer are oxidized into oxide material which forms a smooth and wavy layer with the discontinuous polysilicon layer; and etching said oxide material so as to form smooth hemispherical grooves on the walls of the trench region.

Abstract: A process of forming a high-k dielectric in an integrated circuit structure is disclosed. The process cleans a substrate to remove residual organic materials and strip native oxide from the surface of the substrate. Next, the process introduces precursors on the substrate in molar ratios consistent with formation of dielectric glass films. Following that, the process oxidizes the precursors, heats the precursors, and cools the precursors at a rate that avoids crystallization of the precursors.

Abstract: A method and structure for an integrated circuit structure that includes introducing precursors on a substrate, oxidizing the precursors and heating the precursors. The introducing and the oxidizing of the precursors is preformed in a manner so as to form an amorphous glass dielectric on the substrate. The process preferably includes, before introducing the precursors on the substrate, cleaning the substrate. The introducing of precursors is performed in molar ratios consistent with formation of glass films and may comprise an atomic level chemical vapor on of glass films and may comprise an atomic level chemical vapor deposition of La2O3 and Al2O3 using ratios between 20%-50% La2O3 and 50%-80% Al2O3.

Abstract: A method of depositing a biaxially textured metal oxide on a substrate defining a plane in which metal oxide atoms are vaporized from a source to form a plume of metal oxide atoms. Atoms in the plume disposed at a selected angle in a predetermined range of angles to the plane of the substrate are allowed to contact the substrate while preventing atoms outside a selected angle from reaching the substrate. The preferred range of angles is 40°-70° and the preferred angle is 60°±5°. A moving substrate is disclosed.